| Towards Hardware Accelerated Garbage Collection with Near-Memory Processing | 0 | 0.34 | 2022 |
| HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures | 1 | 0.36 | 2022 |
| Automated High-Level Generation of Low-Power Approximate Computing Circuits | 5 | 0.44 | 2019 |
| Energy-efficient and Sustainable Computing across the Hardware/Software Stack | 0 | 0.34 | 2019 |
| Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis | 0 | 0.34 | 2019 |
| Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018). | 0 | 0.34 | 2019 |
| Attacking memory-hard scrypt with near-data-processing | 0 | 0.34 | 2019 |
| Robust object estimation using generative-discriminative inference for secure robotics applications | 0 | 0.34 | 2018 |
| Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. | 0 | 0.34 | 2018 |
| Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). | 0 | 0.34 | 2018 |
| Towards The Simulation Based Design And Validation Of Mobile Robotic Cyber-Physical Systems | 0 | 0.34 | 2018 |
| A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. | 0 | 0.34 | 2018 |
| Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. | 2 | 0.38 | 2017 |
| Comprehensive comparison of gradient-based cross-spectral stereo matching generated disparity maps | 0 | 0.34 | 2017 |
| Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. | 13 | 0.59 | 2017 |
| Evaluating critical bits in arithmetic operations due to timing violations | 1 | 0.35 | 2017 |
| Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks. | 10 | 0.52 | 2017 |
| A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots | 1 | 0.35 | 2017 |
| Hardware acceleration of feature detection and description algorithms on low-power embedded platforms | 5 | 0.46 | 2016 |
| A fast simulator for the analysis of sub-threshold thermal noise transients | 1 | 0.36 | 2016 |
| Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off. | 8 | 0.63 | 2016 |
| Using Existing Reconfigurable Logic in 3D Die Stacks for Test | 0 | 0.34 | 2016 |
| A low-power dynamic divider for approximate applications. | 6 | 0.50 | 2016 |
| Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. | 1 | 0.39 | 2016 |
| Design of Error-Resilient Logic Gates with Reinforcement Using Implications. | 2 | 0.38 | 2016 |
| Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems | 0 | 0.34 | 2015 |
| A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits | 2 | 0.38 | 2015 |
| DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications | 29 | 1.24 | 2015 |
| Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems | 3 | 0.41 | 2015 |
| Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution | 4 | 0.43 | 2015 |
| Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators | 4 | 0.44 | 2014 |
| ABACUS: a technique for automated behavioral synthesis of approximate computing circuits | 41 | 1.45 | 2014 |
| Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs | 0 | 0.34 | 2013 |
| “Scaling” the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation | 2 | 0.44 | 2013 |
| Flexible data allocation for scratch-pad memories to reduce NBTI effects | 2 | 0.36 | 2013 |
| A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic | 4 | 0.54 | 2012 |
| NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems | 4 | 0.44 | 2012 |
| Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators | 3 | 0.44 | 2012 |
| Using implications to choose tests through suspect fault identification | 4 | 0.39 | 2012 |
| High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System | 4 | 0.52 | 2012 |
| Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems | 6 | 0.42 | 2011 |
| Enhancing Online Error Detection Through Area-Efficient Multi-Site Implications | 7 | 0.51 | 2011 |
| A novel parallel Tier-1 coder for JPEG2000 using GPUs | 9 | 0.68 | 2011 |
| Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis | 2 | 0.37 | 2011 |
| SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs | 8 | 0.52 | 2011 |
| Temperature-Insensitive Dual- Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence | 1 | 0.36 | 2010 |
| Dual-Vt assignment policies in ITD-aware synthesis | 0 | 0.34 | 2010 |
| Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010 | 90 | 6.55 | 2010 |
| Improving the testability and reliability of sequential circuits with invariant logic | 1 | 0.35 | 2010 |
| Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices | 0 | 0.34 | 2010 |
