Name
Abstract | ||
|---|---|---|
A boosted bit line program scheme is proposed tor low operating voltage in the (MLC) NAND Hash memory Our BL to BL boosting scheme. which uses the BL coupling capacitance. is applied to achieve a higher channel potential than is possible with V-cc. so that the V-pass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2 7 V V-cc In the case of 1 8 V V-cc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2 7 V V-cc. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transele.E93.C.423 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | DocType | Volume |
bit line, coupling capacitance, V-pass window margin, boosted channel | Journal | E93C |
Issue | ISSN | Citations |
3 | 0916-8524 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Youngsun Song | 1 | 1 | 1.37 |
| Ki-Tae Park | 2 | 197 | 19.35 |
| Myounggon Kang | 3 | 9 | 5.59 |
| Yunheub Song | 4 | 8 | 2.34 |
| Sungsoo Lee | 5 | 21 | 6.62 |
| Young-Ho Lim | 6 | 81 | 17.55 |
| Kang-Deog Suh | 7 | 56 | 22.19 |