Name
Abstract | ||
|---|---|---|
In this paper, we discuss and analyze the effectiveness of redundancy (also known as digital error correction) and its relationship with DAC settling time, comparator delay, digital logic delay and sampling rate in successive-approximation-register (SAR) ADCs. Behavioral models of SAR ADCs are developed that are four orders of magnitude faster than simulations done in FastSPICE, to predict ADC time progression and to quickly identify the maximum sampling rate that can be used in both redundant and non-redundant cases. We show that redundancy does not always improve sampling rate; instead, the maximum sampling rate depends on the relative magnitudes of different ADC delay components. SPICE simulation in a 65nm CMOS process verifies our behavioral simulation results. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/1973009.1973066 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
different adc delay component,comparator delay,adc time progression,spice simulation,redundancy,sampling rate,maximum sampling rate,digital error correction,digital logic delay,behavioral model,behavioral simulation result,sar adcs,digital logic,behavior modeling,error correction | Flight dynamics (spacecraft),Comparator,Computer science,Spice,Settling time,Sampling (signal processing),Digital error correction,Real-time computing,Electronic engineering,Redundancy (engineering),Boolean algebra | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Albert H. Chang | 1 | 2 | 0.75 |
| Hae-Seung Lee | 2 | 368 | 55.22 |
| Duane Boning | 3 | 201 | 49.37 |