Name
Abstract | ||
|---|---|---|
The IA-64 architecture has a rich set of features including control and data speculation, predication, large register files, and an advanced branch architecture, which allow the compiler to exploit instruction-level parallelism (ILP) and optimize applications in many new ways. The Intel IA-64 compiler incorporates i) state-of-the-art optimization techniques known in the compiler community, ii) optimization techniques that are extended to exploit the resources and features in IA-64, and iii) new optimization techniques designed for IA-64. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/40.888704 | IEEE Micro |
Keywords | Field | DocType |
advanced branch architecture,optimization technique,data speculation,new optimization technique,instruction-level parallelism,ia-64 architecture,advanced optimizer,state-of-the-art optimization technique,compiler community,intel ia-64 compiler,new way,floating point,floating point arithmetic | Integer,Architecture,Computer science,Floating point,Floating-point unit,Scalar (physics),Parallel computing,Real-time computing,Binary scaling,IA-64 | Journal |
Volume | Issue | ISSN |
20 | 6 | 0272-1732 |
Citations | PageRank | References |
34 | 2.15 | 8 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rakesh Krishnaiyer | 1 | 174 | 19.65 |
| Dattatraya Kulkarni | 2 | 70 | 7.50 |
| Daniel Lavery | 3 | 38 | 2.74 |
| Wei Li | 4 | 87 | 5.83 |
| Chu-Cheow Lim | 5 | 168 | 14.45 |
| John Ng | 6 | 34 | 2.15 |
| David Sehr | 7 | 266 | 14.52 |