Name
Abstract | ||
|---|---|---|
Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequential circuits. To reduce the power consumption of clock tree, previous work has shown that clock control logic should be synthesized in the high-level synthesis stage. However, previous work may suffer from a large circuit area overhead on the clock control logic. In this paper, we present an ILP (integer linear programming) formulation to consider both the clock tree and the clock control logic. Our optimization goal is not only to conform to the constraint on the overall power consumption, but also to minimize the area overhead of clock control logic. Compared with previous work, benchmark data show that our approach can greatly reduce the circuit area overhead under the same constraint on the overall power consumption. |
Year | Venue | Keywords |
|---|---|---|
2012 | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING | electronic design automation,high-level synthesis,clock gating,sequential circuits,area minimization |
Field | DocType | Volume |
Clock gating,Computer science,Underclocking,Parallel computing,Clock domain crossing,Synchronous circuit,Clock skew,Digital clock manager,Computer hardware,CPU multiplier,Asynchronous circuit,Distributed computing | Journal | 28 |
Issue | ISSN | Citations |
5 | 1016-2364 | 2 |
PageRank | References | Authors |
0.36 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shih-Hsu Huang | 1 | 203 | 38.89 |
| Wen-Pin Tu | 2 | 21 | 4.32 |
| Bing-Hung Li | 3 | 2 | 0.36 |