Name
Abstract | ||
|---|---|---|
As the design complexity and the number of gates per pin are increasing rapidly, functional verification has become a critical step in the development of a system-on-chip (SoC). Traditional verification techniques, such as simulation or emulation, cannot satisfy the debugging requirement and simulation speed. Among various verification technologies, pattern-based emulation provides the most efficient execution speed, but has limited observability due to the limit on the number of available pins and memory size. In addition, it takes a long time to dump patterns into memory. We propose an efficient pattern-based emulation approach that combines a cycle-based simulation, an input pattern reduction method based on coverage result, and an automatic pattern comparing scheme. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/IWSOC.2005.55 | IWSOC |
Keywords | Field | DocType |
automatic pattern comparing scheme,input pattern reduction method,automatic test pattern generation,efficient execution speed,system-on-chip,pattern-based emulation,functional verification,traditional verification technique,cycle-based simulation,integrated circuit design,memory size,ieee standards,simulation speed,ieee 802.11a baseband,efficient pattern-based emulation,automatic pattern,formal verification,efficient pattern-based emulation approach,various verification technology,satisfiability,system on chip,baseband,observability,acceleration,emulation,system on a chip,debugging,ofdm | Automatic test pattern generation,Functional verification,System on a chip,Computer science,Semulation,Emulation,Integrated circuit design,Embedded system,Hardware emulation,Debugging | Conference |
ISBN | Citations | PageRank |
0-7695-2403-6 | 0 | 0.34 |
References | Authors | |
4 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Il-Gu Lee | 1 | 49 | 9.40 |
| Heejung Yu | 2 | 154 | 22.19 |
| Sok-kyu Lee | 3 | 95 | 23.78 |
| Jin Lee | 4 | 0 | 0.34 |
| Sin-Chong Park | 5 | 80 | 22.58 |