Paper Info
Title
Customization of Register File Banking Architecture for Low Power
Abstract
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application specific customization of register file banking structure. First, we propose two techniques based on (i) profiling and (ii) static application analysis to arrive at a customized energy-efficient bank configuration for a given application on a dual bank register file. We also propose a technique to extend the exploration to a multi-bank register file architecture and an associated register allocation algorithm for further power reduction. This reduces register file power consumption by allocating variables in frequently accessed basic blocks to separate appropriately sized register file bank of active registers. Experimental results indicate that our customized dual bank configuration inferred by both techniques gives energy savings of 40% over a monolithic register file, and the multi-bank register file customization gives a further 15-20% energy savings.
Year
DOI
Venue
2007
10.1109/VLSID.2007.58
VLSI Design
Keywords
Field
DocType
embedded systems,logic design,low-power electronics,microprocessor chips,shift registers,application specific customization,customized energy-efficient bank configuration,dual bank register file,embedded processor based systems,monolithic register files,multibank register file architecture,register allocation,register file banking architecture,register file power consumption,static application analysis
Status register,Register allocation,Memory data register,Computer science,Control register,Stack register,Register file,Processor register,Computer hardware,Computer file
Conference
ISSN
ISBN
Citations 
1063-9667
0-7695-2762-0
4
PageRank 
References 
Authors
0.41
7
3
Name
Order
Citations
PageRank
Rakesh Nalluri140.41
Rohan Garg2284.72
Preeti Ranjan Panda378689.40