| CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance | 0 | 0.34 | 2022 |
| A dual-stage advanced deep learning algorithm for long-term and long-sequence prediction for multivariate financial time series | 0 | 0.34 | 2022 |
| CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems | 1 | 0.35 | 2022 |
| NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory | 0 | 0.34 | 2022 |
| FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies | 0 | 0.34 | 2022 |
| CASES '21: Proceedings of the 2021 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Virtual Event, October 8 - 15, 2021. | 0 | 0.34 | 2021 |
| Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications | 0 | 0.34 | 2019 |
| Reusing Trace Buffers as Victim Caches. | 1 | 0.36 | 2018 |
| Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network. | 1 | 0.36 | 2017 |
| Reusing trace buffers to enhance cache performance. | 2 | 0.37 | 2017 |
| A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. | 0 | 0.34 | 2017 |
| Extending trace history through tapered summaries in post-silicon validation. | 0 | 0.34 | 2016 |
| Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures. | 0 | 0.34 | 2016 |
| A Generic Implementation of Barriers Using Optical Interconnects | 2 | 0.38 | 2016 |
| Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network | 2 | 0.37 | 2016 |
| Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation--Based QRD | 1 | 0.34 | 2016 |
| Area-Aware Cache Update Trackers for Postsilicon Validation. | 0 | 0.34 | 2016 |
| Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory-Based Architectures. | 3 | 0.40 | 2016 |
| Energy efficient FFT implementation through stage skipping and merging | 0 | 0.34 | 2015 |
| Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects | 1 | 0.37 | 2015 |
| Power Optimization Techniques for DDR3 SDRAM | 0 | 0.34 | 2015 |
| Array Interleaving—An Energy-Efficient Data Layout Transformation | 4 | 0.42 | 2015 |
| Energy efficient data flow transformation for givens rotation based QR decomposition | 1 | 0.36 | 2014 |
| High level energy modeling of controller logic in data caches | 0 | 0.34 | 2014 |
| Shared-port register file architecture for low-energy VLIW processors | 4 | 0.40 | 2014 |
| Energy optimization in android applications through wakelock placement | 7 | 0.55 | 2014 |
| Space sensitive cache dumping for post-silicon validation | 0 | 0.34 | 2013 |
| SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems | 4 | 0.48 | 2013 |
| Integrating software caches with scratch pad memory | 6 | 0.46 | 2012 |
| Efficient on-line algorithm for maintaining k-cover of sparse bit-strings. | 0 | 0.34 | 2012 |
| Exploiting UML based validation for compliance checking of TLM 2 based models | 2 | 0.40 | 2012 |
| Exploiting temporal decoupling to accelerate trace-driven NoC emulation | 1 | 0.40 | 2011 |
| A UML based framework for efficient validation of TLM 2 models. | 0 | 0.34 | 2011 |
| Guest Editorial: Special Issue on VLSI Design and Embedded Systems | 0 | 0.34 | 2010 |
| Enhancing Post-Silicon Processor Debug With Incremental Cache State Dumping | 1 | 0.35 | 2010 |
| Front-End Design Flows for Systems on Chip: An Embedded Tutorial | 1 | 0.45 | 2010 |
| Rank based dynamic voltage and frequency scaling fortiled graphics processors | 5 | 0.63 | 2010 |
| FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation | 2 | 0.42 | 2010 |
| Online cache state dumping for processor debug | 6 | 0.45 | 2009 |
| A Special Issue On The "22nd Ieee International Conference On Vlsi Design" New Delhi, India, 5-9 January 2009 | 0 | 0.34 | 2009 |
| A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors | 6 | 0.55 | 2009 |
| Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine | 3 | 0.39 | 2009 |
| Guest editor introduction: special issue on muitiprocessor-based embedded systems | 0 | 0.34 | 2008 |
| Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors | 6 | 0.55 | 2008 |
| REWIRED: REgister Write Inhibition by REsource Dedication | 1 | 0.35 | 2008 |
| Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures | 9 | 0.63 | 2007 |
| The impact of loop unrolling on controller delay in high level synthesis | 10 | 0.67 | 2007 |
| An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform | 5 | 0.52 | 2007 |
| Customization of Register File Banking Architecture for Low Power | 4 | 0.41 | 2007 |
| Power Reduction in VLIW Processor with Compiler Driven Bypass Network | 12 | 0.71 | 2007 |
