Name
Title | ||
|---|---|---|
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing |
Abstract | ||
|---|---|---|
Robust circuit design techniques with respect to soft errors gain importance in the era of very deep submicron technologies. On-line testing will play an important role towards this direction. In this paper we propose a hierarchical architecture for concurrent soft error detection. This architecture is based on current sensing techniques and provides very low area overhead, small detection times and negligible performance penalty on the funtional circuit under check. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/OLT.2002.1030184 | IOLTW |
Keywords | Field | DocType |
CMOS memory circuits,SPICE,SRAM chips,built-in self test,current comparators,current mirrors,error detection,fault diagnosis,fault tolerant computing,integrated circuit testing,radiation hardening (electronics),CMOS technology,SPICE simulation,combinational circuit,concurrent soft error detection,current mirrors,current sensing,hierarchical architecture,low area overhead,on-line testing,retry cycle,robust circuit design,sensing comparator,single event upsets,small detection times,soft error tolerance,time redundancy,transient faults | Architecture,Current mirror,Spice,Computer science,Circuit design,Real-time computing,Electronic engineering,Error detection and correction,Soft error detection,Built-in self-test | Conference |
ISBN | Citations | PageRank |
0-7695-1641-6 | 8 | 1.36 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Y. Tsiatouhas | 1 | 68 | 11.07 |
| A. Arapoyanni | 2 | 39 | 11.46 |
| D. Nikolos | 3 | 291 | 31.38 |
| Th. Haniotakis | 4 | 43 | 7.74 |