AUCTSP: an improved biomarker gene pair class predictor. | 1 | 0.39 | 2018 |
LFSR-based test-data compression with self-stoppable seeds | 6 | 0.48 | 2009 |
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability | 22 | 0.69 | 2008 |
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains | 21 | 0.83 | 2008 |
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores | 30 | 0.91 | 2007 |
A core generator for arithmetic cores and testing structures with a network interface | 4 | 0.57 | 2006 |
Efficient test-data compression for IP cores using multilevel Huffman coding | 4 | 0.49 | 2006 |
Diophantine-Equation Based Arithmetic Test Set Embedding | 7 | 0.53 | 2006 |
Efficient Multiphase Test Set Embedding for Scan-based Testing | 5 | 0.44 | 2006 |
Reseeding-Based Test Set Embedding with Reduced Test Sequences | 9 | 0.61 | 2005 |
Low Power Testing by Test Vector Ordering with Vector Repetition | 3 | 0.42 | 2004 |
Accumulator based Test-per-Scan BIST | 1 | 0.40 | 2004 |
A new test pattern generator for high defect coverage in a BIST environment | 3 | 0.42 | 2004 |
Multiphase BIST: a new reseeding technique for high test-data compression | 15 | 0.76 | 2004 |
Modified Booth Modulo 2^n-1 Multipliers | 11 | 1.01 | 2004 |
A highly regular multi-phase reseeding technique for scan-based BIST | 1 | 0.36 | 2003 |
A ROMless LFSR reseeding scheme for scan-based BIST | 6 | 0.48 | 2002 |
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing | 8 | 1.36 | 2002 |
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register | 6 | 0.55 | 2002 |
A new technique for IDDQ testing in nanometer technologies | 0 | 0.34 | 2002 |
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers | 0 | 0.34 | 2001 |
A novel reseeding technique for accumulator-based test pattern generation | 2 | 0.37 | 2001 |
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores | 3 | 0.43 | 2001 |
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands | 1 | 0.57 | 2001 |
Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes | 0 | 0.34 | 2000 |
Low Power BIST for Wallace Tree-Based Fast Multipliers | 1 | 0.43 | 2000 |
On Testability of Multiple Precharged Domino Logic | 0 | 0.34 | 2000 |
On Path Delay Fault Testing of Multiplexer - Based Shifters | 0 | 0.34 | 1999 |
New efficient totally self-checking Berger code checkers | 4 | 0.52 | 1999 |
Path delay fault testing of ICs with embedded intellectual property blocks | 2 | 0.39 | 1999 |
Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping | 1 | 0.35 | 1999 |
Modular TSC checkers for Bose-Lin and Bose codes | 4 | 0.42 | 1999 |
Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers | 1 | 0.37 | 1999 |
An Accumulator-Based BIST Approach for Two-Pattern Testing | 7 | 0.47 | 1999 |
Self-exercising self testing k-order comparators | 5 | 0.56 | 1997 |
Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches. | 2 | 0.40 | 1996 |
Accumulator-based BIST approach for stuck-open and delay fault testing | 13 | 1.13 | 1995 |
Testing combinational iterative logic arrays for realistic faults | 4 | 0.70 | 1995 |
An efficient comparative concurrent Built-In Self-Test technique | 4 | 0.95 | 1995 |
Efficient Totally Self-Checking Checkers for a Class of Borden Codes | 2 | 0.42 | 1995 |
Efficient fault tolerant cache memory design | 6 | 0.58 | 1995 |
Theory and design of t-error correcting, k-error detecting and d-unidirectional error detecting codes with d >k>t | 5 | 0.61 | 1992 |
Theory and design of t-error correcting/d-error detecting (d>t) and all unidirectional error detecting codes | 8 | 0.88 | 1991 |
Efficient Modular Design of TSC Checkers for M-out-of-2M-Codes | 17 | 2.34 | 1988 |
Efficient modular design of TSC checkers for m-out-of-2m codes | 7 | 0.76 | 1986 |
Systematic t-Error Correcting/All Unidirectional Error Detecting Codes | 29 | 4.34 | 1984 |