Name
Papers
Collaborators
D. NIKOLOS
46
47
Citations 
PageRank 
Referers 
291
31.38
437
Referees 
References 
574
508
Search Limit
100574
Title
Citations
PageRank
Year
AUCTSP: an improved biomarker gene pair class predictor.10.392018
LFSR-based test-data compression with self-stoppable seeds60.482009
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability220.692008
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains210.832008
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores300.912007
A core generator for arithmetic cores and testing structures with a network interface40.572006
Efficient test-data compression for IP cores using multilevel Huffman coding40.492006
Diophantine-Equation Based Arithmetic Test Set Embedding70.532006
Efficient Multiphase Test Set Embedding for Scan-based Testing50.442006
Reseeding-Based Test Set Embedding with Reduced Test Sequences90.612005
Low Power Testing by Test Vector Ordering with Vector Repetition30.422004
Accumulator based Test-per-Scan BIST10.402004
A new test pattern generator for high defect coverage in a BIST environment30.422004
Multiphase BIST: a new reseeding technique for high test-data compression150.762004
Modified Booth Modulo 2^n-1 Multipliers111.012004
A highly regular multi-phase reseeding technique for scan-based BIST10.362003
A ROMless LFSR reseeding scheme for scan-based BIST60.482002
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing81.362002
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register60.552002
A new technique for IDDQ testing in nanometer technologies00.342002
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers00.342001
A novel reseeding technique for accumulator-based test pattern generation20.372001
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores30.432001
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands10.572001
Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes00.342000
Low Power BIST for Wallace Tree-Based Fast Multipliers10.432000
On Testability of Multiple Precharged Domino Logic00.342000
On Path Delay Fault Testing of Multiplexer - Based Shifters00.341999
New efficient totally self-checking Berger code checkers40.521999
Path delay fault testing of ICs with embedded intellectual property blocks20.391999
Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping10.351999
Modular TSC checkers for Bose-Lin and Bose codes40.421999
Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers10.371999
An Accumulator-Based BIST Approach for Two-Pattern Testing70.471999
Self-exercising self testing k-order comparators50.561997
Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches.20.401996
Accumulator-based BIST approach for stuck-open and delay fault testing131.131995
Testing combinational iterative logic arrays for realistic faults40.701995
An efficient comparative concurrent Built-In Self-Test technique40.951995
Efficient Totally Self-Checking Checkers for a Class of Borden Codes20.421995
Efficient fault tolerant cache memory design60.581995
Theory and design of t-error correcting, k-error detecting and d-unidirectional error detecting codes with d >k>t50.611992
Theory and design of t-error correcting/d-error detecting (d>t) and all unidirectional error detecting codes80.881991
Efficient Modular Design of TSC Checkers for M-out-of-2M-Codes172.341988
Efficient modular design of TSC checkers for m-out-of-2m codes70.761986
Systematic t-Error Correcting/All Unidirectional Error Detecting Codes294.341984