Title | ||
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A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture |
Abstract | ||
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We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 × 288) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8×3.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 μW in a QCIF 15-fps sequence with one reference picture. |
Year | DOI | Venue |
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2006 | 10.1093/ietfec/e89-a.12.3623 | IEICE Transactions |
Keywords | Field | DocType |
low power,vlsi-oriented block partitioning strategy,motion estimation,h.264,systolic-array architecture,15-fps sequence,block mode,qcif 15-fps sequence,low-power simd,reference picture,systolic array,130-nm cmos technology,reference frame,vlsi-oriented block,estimation processor core,simd,systolic-array datapath architecture,proposed processor,sub-mw h.264 baseline-profile motion | Reference frame,Datapath,Computer science,Parallel computing,Systolic array,SIMD,CMOS,Motion estimation,Multi-core processor,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
E89-A | 12 | 1745-1337 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
9 |
Name | Order | Citations | PageRank |
---|---|---|---|
Junichi Miyakoshi | 1 | 78 | 17.73 |
Yuichiro Murachi | 2 | 38 | 5.35 |
Tetsuro Matsuno | 3 | 26 | 4.50 |
Masaki Hamamoto | 4 | 19 | 5.17 |
Takahiro Iinuma | 5 | 0 | 1.01 |
Tomokazu Ishihara | 6 | 1 | 1.41 |
Hiroshi Kawaguchi | 7 | 37 | 21.08 |
Masayuki Miyama | 8 | 98 | 20.67 |
Masahiko Yoshimoto | 9 | 0 | 0.34 |