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HIROSHI KAWAGUCHI
Author Info
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Name
Affiliation
Papers
HIROSHI KAWAGUCHI
Kobe Univ, Dept Comp Sci & Syst Engn, Kobe, Hyogo 6578501, Japan
52
Collaborators
Citations
PageRank
162
37
21.08
Referers
Referees
References
162
531
158
Search Limit
100
531
Publications (52 rows)
Collaborators (100 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Greedy Search Algorithm for Mixed Precision in Post-Training Quantization of Convolutional Neural Network Inspired by Submodular Optimization.
0
0.34
2021
A High-Speed Neural Architecture Search Considering the Number of Weights.
0
0.34
2021
A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection
0
0.34
2020
A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations
0
0.34
2020
Heartbeat Interval Error Compensation Method For Low Sampling Rates Photoplethysmography Sensors
0
0.34
2020
Low-Power Photoplethysmography Sensor using Current Integration Circuit for Heartbeat Interval Acquisition.
0
0.34
2019
Non-Contact Instantaneous Heart Rate Extraction System Using 24-Ghz Microwave Doppler Sensor
0
0.34
2019
28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning
0
0.34
2018
Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning
0
0.34
2018
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668].
0
0.34
2018
Hardware Implementation of Autoregressive Model Estimation Using Burg’s Method for Low-Energy Spectral Analysis
0
0.34
2018
Delayed Weight Update for Faster Convergence in Data-Parallel Deep Learning.
0
0.34
2018
A 11.3-Mu A Physical Activity Monitoring System Using Acceleration And Heart Rate
0
0.34
2018
FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature
1
0.36
2017
Wearable pulse wave velocity sensor using flexible piezoelectric film array.
0
0.34
2017
Capacitively coupled ECG sensor system with digitally assisted noise cancellation for wearable application.
0
0.34
2017
Non-contact biometric identification and authentication using microwave Doppler sensor.
0
0.34
2017
A Low Power, Vlsi Object Recognition Processor Using Sparse Find Feature For 60 Fps Hdtv Resolution Video
0
0.34
2017
A 28-Nm 484-Fj/Writecycle 650-Fj/Readcycle 8t Three-Port Fd-Soi Sram For Image Processor
0
0.34
2016
Adaptive noise cancellation method for capacitively coupled ECG sensor using single insulated electrode
0
0.34
2016
A negative-resistance sense amplifier for low-voltage operating STT-MRAM
2
0.37
2015
Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation For Wearable Healthcare Systems
0
0.34
2015
A Low Power 6t-4c Non-Volatile Memory Using Charge Sharing And Non-Precharge Techniques
0
0.34
2015
Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector
3
0.70
2015
A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor.
0
0.34
2015
A Low-Latency Dmr Architecture With Fast Checkpoint Recovery Scheme
0
0.34
2015
A ferroelectric-based non-volatile flip-flop for wearable healthcare systems
0
0.34
2015
Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path.
0
0.34
2015
A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems
3
0.60
2014
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability
7
0.55
2014
Stt-Mram Operating At 0.38 V Using Negative-Resistance Sense Amplifier
0
0.34
2014
A 40-Nm Resilient Cache Memory For Dynamic Variation Tolerance Delivering X91 Failure Rate Improvement Under 35% Supply Voltage Fluctuation
0
0.34
2014
An Opampless Second-Order Mash Delta Sigma Adc With Using Gated Ring Oscillator Time-To-Digital Converter
0
0.34
2013
A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition
3
0.44
2013
A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system
4
0.57
2013
A 168-Mw 2.4x-Real-Time 60-Kword Continuous Speech Recognition Processor Vlsi
0
0.34
2013
A 40-Nm 256-Kb Half-Select Resilient 8t Sram With Sequential Writing Technique
1
0.37
2012
A 0.15-Mu M Fd-Soi Substrate Bias Control Sram With Inter-Die Variability Compensation Scheme
0
0.34
2012
Neutron-induced soft error rate estimation for SRAM using PHITS
1
0.36
2012
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme
2
0.42
2012
Bit-Error And Soft-Error Resilient 7t/14t Sram With 150-Nm Fd-Soi Process
0
0.34
2012
Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores.
0
0.34
2012
7t Sram Enabling Low-Energy Instantaneous Block Copy And Its Application To Transactional Memory
0
0.34
2011
A Low-Power Multi-Phase Oscillator With Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
3
0.54
2011
A 58-Mu W Single-Chip Sensor Node Processor With Communication Centric Design
0
0.34
2010
A 433-Mhz Rail-To-Rail Voltage Amplifier With Carrier Sensing Function For Wireless Sensor Networks
0
0.34
2009
An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.
0
0.34
2008
Counter-Based Broadcasting With Hop Count Aware Random Assessment Delay Extension For Wireless Sensor Networks
1
0.35
2008
Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme
0
0.34
2007
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture
0
0.34
2006
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