Paper Info
Title
Optimization of Embedded Controllers Based on Redundant Transition Removal and Fault Simulation Using k-WISE Tests
Abstract
This paper presents an efficient redundancy removal technique for hierarchical optimization of FSM networks. In this technique, we first remove redundant transitions from the state transition graph (STG) of the driven FSM, M-2, of the cascaded network by applying a reachability analysis to the composite machine, M-1 --> M-2, once and for all. Then, a k-wise complete test suite for M2 is generated from the new STG of the driven FSM. Redundancy identification consists of two phases. In the first phase, almost all of the detectable stuck-at faults are identified by fault simulation using the k-wise test suite. During the second phase, each fault f that is undetected by k-wise tests is injected in M-2 to obtain M-2(f) in the topologically sorted order one by one. Then the equivalence check of two FSMs M-2 and M-2(f) in the environment where M-2 (M-2(f)) is driven by M-1 is done. If a fault is found to be undetectable in the second phase, it is a redundant fault and kept in M-2 (M-2(f) is taken as M-2). Finally, simultaneous removal of redundant faults is done at logic level. We present experimental results to provide a comparison of the data produced by the state-of-the-art FSM network optimizer and show the effectiveness of our approach.
Year
DOI
Venue
2009
10.1142/S0218126609005174
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
Keywords
Field
DocType
Hierarchical optimization,FSM networks,redundancy removal,combinatorial covering test
Test suite,Graph,Computer science,Parallel computing,Algorithm,Reachability,Equivalence (measure theory),Redundancy (engineering),Logic level
Journal
Volume
Issue
ISSN
18
4
0218-1266
Citations 
PageRank 
References 
0
0.34
1
Authors
1
Name
Order
Citations
PageRank
Sezer Gören16411.62