Sezer Gören - Citegraph

Author Info

Name	Affiliation	Papers
SEZER GÖREN	Department of Computer Engineering, Bahcesehir University, Ciragan Cad. Osmanpasa, Mektebi Sok, Besiktas 34349, Istanbul, Turkey	28
Collaborators	Citations	PageRank
54	64	11.62
Referers	Referees	References
147	427	201

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100427

Publications (28 rows)

Collaborators (54 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Lossless Look-Up Table Compression for Hardware Implementation of Transcendental Functions	0	0.34	2019
Tools and Techniques for Implementation of Real-time Video Processing Algorithms	0	0.34	2019
Semi- and Fully-Random Access LUTs for Smooth Functions.	0	0.34	2019
Precise Vehicle Positioning for Indoor Navigation via OpenXC.	0	0.34	2018
Efficient Combinational Circuits for Division by Small Integer Constants	1	0.38	2016
Output Domain Downscaler.	1	0.36	2016
Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection	1	0.36	2015
An area efficient real time implementation of dual tree complex wavelet transform in field programmable gate arrays	0	0.34	2015
Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet	10	0.65	2014
Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only)	3	0.40	2013
Programmable Hardware Based Short Read Aligner Using Phred Quality Scores	0	0.34	2013
A Fast Circuit Topology for Finding the Maximum of N k-bit Numbers	6	0.50	2013
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors.	1	0.35	2013
Reconfigurable hardware-based genome aligner using quality scores	0	0.34	2013
Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration	6	0.54	2013
FPGA Based Particle Identification in High Energy Physics Experiments	0	0.34	2012
Ultra-fast curve fitting for pulses on FPGA.	0	0.34	2012
FPGA bitstream protection with PUFs, obfuscation, and multi-boot.	2	0.38	2011
Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort	8	0.53	2011
Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization	2	0.37	2010
FPGA design security with time division multiplexed PUFs	2	0.38	2010
Gravitational pose estimation	2	0.38	2010
Defect-Tolerant Logic Mapping for Nanocrossbars Based on Two-Dimensional Sort.	0	0.34	2010
Optimization of Embedded Controllers Based on Redundant Transition Removal and Fault Simulation Using k-WISE Tests	0	0.34	2009
On state reduction of incompletely specified finite state machines	15	1.14	2007
Population-Based FPGA Solution to Mastermind Game	1	0.40	2006
Test sequence generation for controller verification and test with high coverage	0	0.34	2006
Testing Finite State Machines Based on a Structural Coverage Metric	3	0.44	2002