Name
Abstract | ||
|---|---|---|
Recent improvements in design verification strive to automate the error-detection process and greatly enhance engineers' ability to detect functional errors. However, the process of diagnosing the cause of these errors and fixing them remains difficult and requires significant ad-hoc manual effort. Our work proposes improvements to this aspect of verification by presenting novel constructs and algorithms to automate the error-repair process at the Register-Transfer Level (RTL), where most development occurs. Our contributions include a new RTL error model and scalable error-repair algorithms. Empirical results show that our solution can diagnose and correct errors in just a handful of minutes even for complex designs o/up to several thousand lines of RTL code in minutes. This demonstrates the superior scalability and efficiency of our approach compared to previous work. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/HLDVT.2007.4392789 | HLDVT |
Keywords | Field | DocType |
ad-hoc manual effort,previous work,design verification,error-detection process,correct error,logic cad,transfer level,automatic error diagnosis,new rtl error model,fault diagnosis,circuit cad,rtl design,scalable error-repair algorithm,functional error-detection process,program verification,rtl code,register-transfer level design verification,error correction,error-repair process,complex de,debugging,error detection,register transfer level | Computer science,Theoretical computer science,Error detection and correction,Real-time computing,Scalability | Conference |
ISSN | ISBN | Citations |
1552-6674 | 978-1-4244-1480-2 | 6 |
PageRank | References | Authors |
0.56 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kai-hui Chang | 1 | 216 | 19.41 |
| Ilya Wagner | 2 | 204 | 10.01 |
| Valeria Bertacco | 3 | 1365 | 86.93 |
| Igor L. Markov | 4 | 3858 | 261.98 |