| PriMax: maximizing DSL application performance with selective primitive acceleration | 0 | 0.34 | 2022 |
| Bypassing Multicore Memory Bugs With Coarse-Grained Reconfigurable Logic | 0 | 0.34 | 2022 |
| Chopin: Composing Cost-Effective Custom Chips with Algorithmic Chiplets | 0 | 0.34 | 2021 |
| MyML: User-Driven Machine Learning | 0 | 0.34 | 2021 |
| Optimizing Vertex Pressure Dynamic Graph Partitioning in Many-core Systems | 0 | 0.34 | 2021 |
| A Defense-Inspired Benchmark Suite | 0 | 0.34 | 2021 |
| Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware | 0 | 0.34 | 2021 |
| Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning | 0 | 0.34 | 2020 |
| Neksus: An Interconnect for Heterogeneous System-In-Package Architectures | 1 | 0.39 | 2020 |
| Thwarting Control Plane Attacks with Displaced and Dilated Address Spaces | 0 | 0.34 | 2020 |
| Collaborative accelerators for in-memory MapReduce on scale-up machines. | 1 | 0.37 | 2019 |
| SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design | 0 | 0.34 | 2019 |
| Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems | 0 | 0.34 | 2018 |
| SWAN: mitigating hardware trojans with design ambiguity | 0 | 0.34 | 2018 |
| Heterogeneous Memory Subsystem for Natural Graph Analytics | 4 | 0.41 | 2018 |
| Symbolic Assertion Mining For Security Validation | 0 | 0.34 | 2018 |
| MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation. | 1 | 0.35 | 2017 |
| Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves. | 14 | 0.62 | 2017 |
| 3DFAR: A three-dimensional fabric for reliable multi-core processors. | 0 | 0.34 | 2017 |
| Energy efficient object detection on the mobile GP-GPU | 1 | 0.34 | 2017 |
| Resource Conscious Diagnosis and Reconfiguration for NoC Permanent Faults. | 2 | 0.37 | 2016 |
| Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification. | 1 | 0.36 | 2016 |
| BugMD: automatic mismatch diagnosis for bug triaging. | 1 | 0.35 | 2016 |
| ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability | 0 | 0.34 | 2015 |
| Post-silicon Validation of Multi-Processor Memory Consistency | 4 | 0.42 | 2015 |
| NoCVision: A Network-on-Chip Dynamic Visualization Solution | 0 | 0.34 | 2015 |
| ItHELPS: Iterative high-accuracy error localization in post-silicon | 0 | 0.34 | 2015 |
| Highly Fault-tolerant NoC Routing with Application-aware Congestion Management | 5 | 0.40 | 2015 |
| ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality | 2 | 0.37 | 2014 |
| DiAMOND:Distributed alteration of messages for on-chip network debug | 1 | 0.34 | 2014 |
| High-radix on-chip networks with low-radix routers | 5 | 0.41 | 2014 |
| Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation | 1 | 0.35 | 2014 |
| Power-Aware NoCs through Routing and Topology Reconfiguration | 25 | 0.82 | 2014 |
| ArChiVED: Architectural checking via event digests for high performance validation | 0 | 0.34 | 2014 |
| Post-silicon platform for the functional diagnosis and debug of networks-on-chip. | 6 | 0.44 | 2014 |
| On the use of GP-GPUs for accelerating compute-intensive EDA applications | 4 | 0.40 | 2013 |
| uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults | 9 | 0.46 | 2013 |
| Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms | 1 | 0.36 | 2013 |
| SAGA: SystemC acceleration on GPU architectures | 16 | 0.85 | 2012 |
| Approximating checkers for simulation acceleration | 3 | 0.40 | 2012 |
| Viper: virtual pipelines for enhanced reliability | 11 | 0.60 | 2012 |
| Humans for EDA and EDA for humans | 1 | 0.34 | 2012 |
| A Reliable Routing Architecture and Algorithm for NoCs | 10 | 0.49 | 2012 |
| SystemC simulation on GP-GPUs: CUDA vs. OpenCL | 5 | 0.45 | 2012 |
| Architectural Trace-Based Functional Coverage for Multiprocessor Verification | 1 | 0.34 | 2012 |
| Bridging pre- and post-silicon debugging with BiPeD | 4 | 0.41 | 2012 |
| Checking architectural outputs instruction-by-instruction on acceleration platforms | 4 | 0.45 | 2012 |
| Highly scalable distributed dataflow analysis | 6 | 0.43 | 2011 |
| Cardio: Adaptive CMPs for reliability through dynamic introspective operation | 1 | 0.35 | 2011 |
| ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment | 50 | 1.17 | 2011 |
