Title
Power-Aware Test Pattern Generation for At-Speed LOS Testing
Abstract
Launch-off-Capture (LOC) and Launch-off-Shift (LOS) are the two main test schemes for at-speed scan delay testing. In the literature, it has been shown that LOS has higher performance than LOC in terms of fault coverage and test length, but higher peak power consumption during the launch-to-capture cycle. Power reduction seems to be the key to really exploit LOS test scheme. However, it has been proven that reducing too much test power can lead to test escape due to under-test. In this context, this study proposes a smart X-filling framework able to adapt peak power consumption during the launch-to-capture cycle according to the functional power, i.e. the power consumption of the circuit in functional mode. Here, the main goal is to obtain a final test set with peak power consumption as close as possible to the functional power. Experimental results, carried out on the well-known ITC'99 benchmarks, prove the feasibility of the proposed approach.
Year
DOI
Venue
2011
10.1109/ATS.2011.50
Asian Test Symposium
Keywords
Field
DocType
power-aware test pattern generation,los test scheme,power reduction,launch-to-capture cycle,higher peak power consumption,final test,at-speed los testing,power consumption,main test scheme,test power,peak power consumption,functional power,testing,vectors,fault coverage,support vector machine,loc,automatic test pattern generation
Automatic test pattern generation,Pattern generation,Fault coverage,Computer science,Exploit,Real-time computing,Electronic engineering,Test compression,Test power,Power consumption,Test set
Conference
ISSN
Citations 
PageRank 
1081-7735
0
0.34
References 
Authors
0
7
Name
Order
Citations
PageRank
A. Bosio111315.51
L. Dilillo2449.49
P. Girard347841.91
A. Todri473.85
A. Virazel516923.25
K. Miyase61166.12
X. Wen700.34