Name
Title | ||
|---|---|---|
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. |
Abstract | ||
|---|---|---|
A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking; and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power. The proposed proportional path decouples the detector quantization error and oscillator noise bandwidth tradeoff and helps maximize bandwidth to suppress dig... |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/JSSC.2011.2157259 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Bandwidth,Jitter,Tuning,Quantization,Phase locked loops,Oscillators,Phase frequency detector | Digitally controlled oscillator,Phase-locked loop,Control theory,Computer science,Phase noise,Electronic engineering,Delta-sigma modulation,Bandwidth (signal processing),Digital-to-analog converter,Jitter,Phase frequency detector | Journal |
Volume | Issue | ISSN |
46 | 8 | 0018-9200 |
Citations | PageRank | References |
9 | 0.83 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wenjing Yin | 1 | 65 | 8.81 |
| Rajesh Inti | 2 | 118 | 13.20 |
| Amr Elshazly | 3 | 242 | 28.08 |
| Brian Young | 4 | 118 | 12.20 |
| Pavan Kumar Hanumolu | 5 | 554 | 84.82 |