Amr Elshazly - Citegraph

Author Info

Name	Affiliation	Papers
AMR ELSHAZLY	School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA	44
Collaborators	Citations	PageRank
89	242	28.08
Referers	Referees	References
700	401	174

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100700

Publications (44 rows)

Collaborators (89 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET	1	0.38	2022
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET	3	0.42	2019
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS.	2	0.37	2018
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.	0	0.34	2018
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.	1	0.36	2017
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC.	1	0.36	2017
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.	12	0.69	2016
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.	6	0.50	2016
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS	0	0.34	2016
High Frequency Buck Converter Design Using Time-Based Control Techniques	11	1.12	2015
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter.	0	0.34	2015
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC	27	1.39	2015
A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links	1	0.37	2015
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method	4	0.49	2015
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS	5	0.71	2015
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links	4	0.48	2015
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS	11	1.38	2015
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS	6	0.81	2014
A 5 Gb/s, 10 ns Power-On-Time, 36 W Off-State Power, Fast Power-On Transmitter for Energy Proportional Links	0	0.34	2014
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS	8	0.67	2014
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques	16	1.08	2014
A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement	2	0.57	2014
A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter	0	0.34	2014
A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators	0	0.34	2014
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop	11	0.66	2014
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with −106dBc/Hz In-band noise using time amplifier based TDC	1	0.39	2014
A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW	0	0.34	2014
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS	3	0.49	2014
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer.	1	0.52	2012
A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators	0	0.34	2012
A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity	2	0.36	2012
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.	31	2.09	2012
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC.	0	0.34	2012
A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control	3	0.54	2012
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS	1	0.40	2011
A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery	10	1.19	2011
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration.	11	1.16	2011
A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance	4	0.52	2011
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration	19	1.41	2011
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking.	9	0.83	2011
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery	1	0.43	2011
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance	1	0.36	2011
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth.	9	1.04	2010
2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing	4	0.49	2006