Name
Abstract | ||
|---|---|---|
The aim of this paper is to present a new approach to creating high performance and low-power asynchronous circuits using high level design tools. In order to achieve this, we introduce a new timing model called Pseudo Delay-Insensitive model. To prove the goodness of this model, we present the results after comparing, for a set of benchmarks, our implementation with other implementations (synchronous and asynchronous). |
Year | Venue | Keywords |
|---|---|---|
2002 | PATMOS | design low-power asynchronous circuits,low-power asynchronous circuit,new timing model,high level design tool,high performance,new methodology,new approach,pseudo delay-insensitive model,asynchronous circuit |
Field | DocType | ISBN |
Asynchronous communication,High-level design,Asynchronous system,Synchronizer,Computer science,High-level synthesis,Algorithm,Circuit design,Synchronous circuit,Computer engineering,Asynchronous circuit,Distributed computing | Conference | 3-540-44143-3 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Oscar Garnica | 1 | 70 | 18.36 |
| Juan Lanchares | 2 | 171 | 23.30 |
| Román Hermida | 3 | 89 | 15.34 |