| Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks. | 6 | 0.48 | 2019 |
| A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. | 0 | 0.34 | 2019 |
| Complexity reduction in the HEVC/H265 standard based on smooth region classification. | 4 | 0.40 | 2018 |
| Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks. | 0 | 0.34 | 2018 |
| A slack-based approach to efficiently deploy radix 8 booth multipliers. | 0 | 0.34 | 2017 |
| Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark | 4 | 0.42 | 2017 |
| A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. | 2 | 0.43 | 2016 |
| Improving circuit performance with multispeculative additive trees in high-level synthesis. | 3 | 0.41 | 2014 |
| Ultra-low-power adder stage design for exascale floating point units | 3 | 0.41 | 2014 |
| A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths | 0 | 0.34 | 2013 |
| Exploring the energy efficiency of Multispeculative Adders. | 1 | 0.36 | 2013 |
| Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials | 4 | 0.44 | 2013 |
| Multispeculative Addition Applied to Datapath Synthesis. | 11 | 0.70 | 2012 |
| Power optimization in heterogenous datapaths. | 0 | 0.34 | 2011 |
| Frequent-pattern-guided multilevel decomposition of behavioral specifications | 0 | 0.34 | 2009 |
| Applying speculation techniques to implement functional units. | 7 | 0.67 | 2008 |
| Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures | 1 | 0.36 | 2006 |
| Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs | 3 | 0.54 | 2005 |
| Behavioural transformation to improve circuit performance in high-level synthesis | 5 | 0.48 | 2005 |
| Behavioural Scheduling to Balance the Bit-Level Computational Effort | 0 | 0.34 | 2004 |
| Annealing placement by thermodynamic combinatorial optimization | 10 | 0.70 | 2004 |
| Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation | 1 | 0.36 | 2002 |
| A New Methodology to Design Low-Power Asynchronous Circuits | 0 | 0.34 | 2002 |
| A study about the efficiency of formal high-level synthesis applied to verification | 0 | 0.34 | 2002 |
| Multiple-Precision Circuits Allocation Independent of Data-Objects Length | 5 | 0.52 | 2002 |
| Transformation of Equational Specification by Means of Genetic Programming | 1 | 0.41 | 2002 |
| Source Code Transformation to Improve Conditional Hardware Reuse | 0 | 0.34 | 2002 |
| High-level synthesis of multiple-precision circuitsindependent of data-objects length. | 0 | 0.34 | 2002 |
| Adaptive FPGA Placement by Natural Optimization | 1 | 0.38 | 2000 |
| Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. | 0 | 0.34 | 2000 |
| Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies | 3 | 0.50 | 1999 |
| A Unified Algorithm for Mutual Exclusiveness Identification | 2 | 0.45 | 1999 |
| RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing | 3 | 0.49 | 1998 |
| Heuristics for branch-and-bound global allocation | 7 | 0.73 | 1992 |
| An approach to minimal-time scheduling of micro-operations | 2 | 0.62 | 1990 |
