Title
A highly integrated and flexible joint test system based on DSP/FPGA-FPGA
Abstract
This paper analyzes that a flexible robot test system should have these properties of data acquisition, servo control, multi-communication modes, complex and fast computation, multitasking and friendly interface. This paper investigates a highly integrated and flexible joint test system for HIT arm based on DSP/FPGA-FPGA. This test system includes two hardware levels, Cartesian level and joint level. The Cartesian level includes a digital signal processing/field programmable gate array (DSP/FPGA) structure. Based on this level, complex control algorithm and fast computation can be carried out; the joint level has the other FPGA, it can realize two joints functions: all sensors data acquisition, servo control. In this test system, there are two communication modes: CAN bus and M-LVDS bus. According to the hardware architecture, a novel software architecture was designed, which consists of three levels: external user level, the higher level and the lower level. This system is flexible, many measures and experiments can be implemented by this system. Experimental results demonstrate the effectiveness of the highly integrated and flexible joint test system.
Year
DOI
Venue
2009
10.1109/ROBIO.2009.5420551
ROBIO
Keywords
Field
DocType
can bus,higher level,digital signal processing/field programmable gate array structure,fast computation,robots,servo control,servomechanisms,flexible joint test system,m-lvds bus,hit arm,dsp,lower level,joint,hardware level,data acquisition,external user level,test system,multitasking,multi-communication modes,fpga,dsp/fpga-fpga,joint level,field programmable gate arrays,cartesian level,flexible robot test system,digital signal processing,hardware,potentiometers,software architecture,hardware architecture,field programmable gate array
CAN bus,Digital signal processing,Data acquisition,Field-programmable gate array,Servo control,Software architecture,Engineering,Computer hardware,Human multitasking,Embedded system,Hardware architecture
Conference
ISBN
Citations 
PageRank 
978-1-4244-4775-6
0
0.34
References 
Authors
5
5
Name
Order
Citations
PageRank
Jin Dang100.34
Fenglei Ni2268.22
Yikun Gu3406.92
Minghe Jin411319.16
Hong Liu521348.37