Paper Info
Title
Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis
Abstract
Multiply-add operations form a crucial part of many digital signal processing and control engineering applications. Since their performance is crucial for the application-level speed-up, it is worthwhile to explore a wide spectrum of implementations alternatives, trading increased area/energy usage to speed-up units on the critical path of the computation. This paper examines existing solutions and proposes two new architectures for floating-point fused multiply-adds, and also considers the impact of different in-fabric features of recent FPGA architectures. The units rely on different degrees of carry-save arithmetic improve performance by up to 2.5x over the closest state-of-the-art competitor. They are evaluated at the application level by modifying an existing high-level synthesis system to automatically insert the new units for computations on the critical path of three different convex solvers.
Year
DOI
Venue
2013
10.1109/IPDPSW.2013.106
IPDPS Workshops
Keywords
Field
DocType
field programmable gate arrays,floating point arithmetic,high level synthesis,FPGA architectures,application-level speed-up,architecture exploration,convex solvers,high-level synthesis,high-performance floating-point fused multiply-add units,in-fabric features,multiply-add operations,state-of-the-art competitor,FMA,FPGA,carry save,floating-point,fused,multiply-add
Multiply–accumulate operation,Digital signal processing,Adder,Computer science,Floating point,High-level synthesis,Field-programmable gate array,Critical path method,Computer hardware,Multiplexing,Computer engineering
Conference
Citations 
PageRank 
References 
0
0.34
0
Authors
3
Name
Order
Citations
PageRank
Bjorn Liebig100.34
Jens Huthmann2364.83
Andreas Koch39415.13