| neoDBMS: In-situ Snapshots for Multi-Version DBMS on Native Computational Storage | 0 | 0.34 | 2022 |
| DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity | 0 | 0.34 | 2022 |
| Near-Data Processing in Database Systems on Native Computational Storage under HTAP Workloads. | 0 | 0.34 | 2022 |
| Cache-Coherent Shared Locking for Transactionally Consistent Updates in Near-Data Processing DBMS on Smart Storage | 0 | 0.34 | 2022 |
| SPNC: An Open-Source MLIR-Based Compiler for Fast Sum-Product Network Inference on CPUs and GPUs | 2 | 0.40 | 2022 |
| The Scale4Edge RISC-V Ecosystem | 0 | 0.34 | 2022 |
| Near-Data Processing in Database Systems on Native Computational Storage under HTAP Workloads. | 0 | 0.34 | 2022 |
| Optimizing a Hardware Network Stack to Realize an In-Network ML Inference Application | 1 | 0.40 | 2021 |
| nKV in Action: Accelerating KV-Stores on NativeComputational Storage with Near-Data Processing. | 0 | 0.34 | 2020 |
| Extending High-Level Synthesis with High-Performance Computing Performance Visualization | 0 | 0.34 | 2020 |
| nKV in Action: Accelerating KV-Stores on NativeComputational Storage with Near-Data Processing. | 0 | 0.34 | 2020 |
| nKV: near-data processing with KV-stores on native computational storage | 0 | 0.34 | 2020 |
| IPA-IDX: In-Place Appends for B-Tree Indices | 1 | 0.36 | 2019 |
| Moving Processing to Data: On the Influence of Processing in Memory on Data Management. | 0 | 0.34 | 2019 |
| Exact and Practical Modulo Scheduling for High-Level Synthesis | 0 | 0.34 | 2019 |
| Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. | 1 | 0.37 | 2019 |
| ILP-Based Modulo Scheduling and Binding for Register Minimization | 0 | 0.34 | 2018 |
| Improved High-Level Synthesis for Complex CellML Models. | 0 | 0.34 | 2018 |
| NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management. | 0 | 0.34 | 2018 |
| GeMS: a generator for modulo scheduling problems: work in progress | 1 | 0.35 | 2018 |
| Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis | 0 | 0.34 | 2013 |
| Hardware/Software Co-Compilation With The Nymble System | 14 | 0.76 | 2013 |
| Preface-ARC | 0 | 0.34 | 2012 |
| Malacoda: towards high-level compilation of network security applications on reconfigurable hardware | 1 | 0.35 | 2012 |
| Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers | 0 | 0.34 | 2012 |
| Evaluation of speculative execution techniques for high-level language to hardware compilation | 5 | 0.54 | 2011 |
| Precore - A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation | 8 | 0.58 | 2011 |
| MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers | 12 | 0.72 | 2011 |
| RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers | 1 | 0.40 | 2011 |
| A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation | 13 | 0.83 | 2010 |
| Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs | 6 | 0.48 | 2009 |
| Efficient Inverse Kinematics Algorithm Based On Conformal Geometric Algebra - Using Reconfigurable Hardware | 9 | 0.79 | 2008 |
| Low-latency high-bandwidth HW/SW communication in a virtual memory environment | 7 | 0.63 | 2008 |
| Memory Access Schemes for Configurable Processors | 12 | 1.08 | 2000 |
