Paper Info
Title
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture
Abstract
A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row method makes column processing parallelism easier to exploit, doubles available row processor parallelism, and significantly simplifies row processors— which results in smaller area, higher speeds, and lower energy dissipation. Simulation results over an additive white Gaussian channel show that the error performance of high row-weight codes with Split-Row decoding is within 0.3-0.6 dB of the Min-Sum and Sum-Product decoding algorithms. A full parallel decoder for a (3,6) LDPC code with a code length of 1536 bits is implemented in a 0.18 µm CMOS technology twice: once using the Split-Row method, and once using the Min-Sum algorithm for comparison. The Split-Row decoder operates at 53 MHz and delivers a throughput of 5.4 Gbps with 15 decoding iterations per block. The Split-Row decoder is about 1.3 times smaller, has an average wire length 1.5 times shorter, and has a throughput 1.6 times higher than the Min-Sum decoder. parity check matrix (5). Full parallel decoders can provide very high throughputs while operating at low clock rates. The major challenge in implementing parallel decoders is the high interconnect complexity between row and column processors. There have been studies to reduce the interconnect complexity by using structured LDPC codes (13) or optimizing mapping techniques (14). In this paper, we propose Split-Row, a reduced complexity decoding method which splits each row module into two nearly-independent simplified halves. This method reduces the wire interconnect complexity between row and column processors and increases parallelism in the row processing stage. The Split-Row method also simplifies row processors which results in an overall smaller decoder. We further propose a mapping method to decrease the interconnect complexity in a full parallel Split-Row decoder. The proposed mapping architecture makes the overall decoder yet smaller, which results in higher clock rates and higher energy efficiency than with traditional mapping methods.
Year
DOI
Venue
2006
10.1109/ICCD.2006.4380835
ICCD
Keywords
Field
DocType
ldpc code,high throughput,energy efficient,decoding,energy dissipation
Dissipation,Low-density parity-check code,Computer science,Parallel computing,CMOS,Soft-decision decoder,Decoding methods,Throughput,Interconnection,Code (cryptography)
Conference
Citations 
PageRank 
References 
7
0.74
13
Authors
2
Name
Order
Citations
PageRank
Tinoosh Mohsenin140647.43
Bevan M. Baas229527.78