| Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" [Integr. VLSI J. 58. (2017) 74-81]. | 0 | 0.34 | 2019 |
| Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding | 0 | 0.34 | 2018 |
| A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding | 0 | 0.34 | 2018 |
| KiloCore: A Fine-Grained 1, 000-Processor Array for Task-Parallel Applications. | 2 | 0.45 | 2017 |
| Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm. | 26 | 1.53 | 2017 |
| KiloCore: A 32-nm 1000-Processor Computational Array. | 18 | 0.81 | 2017 |
| Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs. | 0 | 0.34 | 2017 |
| A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array. | 10 | 0.48 | 2016 |
| KiloCore: A 32 nm 1000-processor array | 1 | 0.41 | 2016 |
| A software LDPC decoder implemented on a many-core array of programmable processors | 0 | 0.34 | 2015 |
| Area Efficient Backprojection Computation With Reduced Floating-Point Word Width For Sar Image Formation | 1 | 0.35 | 2015 |
| Optimizing power of many-core systems by exploiting dynamic voltage, frequency and core scaling | 1 | 0.36 | 2015 |
| Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms | 0 | 0.34 | 2014 |
| Scalable hardware-based power management for many-core systems | 1 | 0.38 | 2014 |
| Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks | 0 | 0.34 | 2014 |
| Parallel AES Encryption Engines for Many-Core Processor Arrays | 18 | 0.87 | 2013 |
| LDPC decoder with an adaptive wordwidth datapath for energy and BER co-optimization | 2 | 0.40 | 2013 |
| A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks. | 1 | 0.35 | 2012 |
| A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture | 2 | 0.39 | 2012 |
| A high-performance area-efficient AES cipher on a many-core platform | 0 | 0.34 | 2011 |
| RoShaQ: High-performance on-chip router with shared queues | 16 | 0.75 | 2011 |
| Low power LDPC decoder with efficient stopping scheme for undecodable blocks | 7 | 0.66 | 2011 |
| A low-area multi-link interconnect architecture for GALS chip multiprocessors | 9 | 0.63 | 2010 |
| A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders | 5 | 0.88 | 2010 |
| Circuit modeling for practical many-core architecture design exploration | 0 | 0.34 | 2010 |
| A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network | 4 | 0.40 | 2009 |
| An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes | 5 | 0.61 | 2009 |
| High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors | 10 | 0.63 | 2009 |
| Multi-Split-Row Threshold decoding implementations for LDPC codes | 13 | 0.93 | 2009 |
| A Low-Cost High-Speed Source-Synchronous Interconnection Technique For Gals Chip Multiprocessors | 4 | 0.40 | 2009 |
| The Design Of A Reconfigurable Continuous-Flow Mixed-Radix Fft Processor | 17 | 1.16 | 2009 |
| A low-area interconnect architecture for chip multiprocessors | 3 | 0.42 | 2008 |
| AsAP: An Asynchronous Array of Simple Processors | 15 | 0.99 | 2008 |
| Architecture and Evaluation of an Asynchronous Array of Simple Processors | 3 | 0.49 | 2008 |
| A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains | 28 | 1.18 | 2007 |
| AsAP: A Fine-Grained Many-Core Platform for DSP Applications | 14 | 0.88 | 2007 |
| A shared memory module for asynchronous arrays of processors | 2 | 0.37 | 2007 |
| Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles | 8 | 0.78 | 2006 |
| An asynchronous array of simple processors for dsp applications | 31 | 3.80 | 2006 |
| Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems | 6 | 0.53 | 2006 |
| Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture | 7 | 0.74 | 2006 |
| A Generalized Cached-Fft Algorithm | 5 | 0.72 | 2005 |
