Name
Abstract | ||
|---|---|---|
In this paper, we present a new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique during BIST. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/VTS.2001.923454 | VTS |
Keywords | Field | DocType |
automatic test pattern generation,built-in self test,clocks,integrated circuit testing,logic testing,low-power electronics,TPG,clock tree,low power BIST test pattern generator,modified clock scheme,switching activity,test operation,test vectors | Automatic test pattern generation,Computer science,System testing,Clock tree,Electronic engineering,Real-time computing,CMOS,Test pattern generators,Energy consumption,Built-in self-test,Low-power electronics | Conference |
ISSN | Citations | PageRank |
1093-0167 | 39 | 2.03 |
References | Authors | |
17 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Girard | 1 | 478 | 41.91 |
| L. Guiller | 2 | 380 | 24.24 |
| C. Landrault | 3 | 52 | 3.07 |
| S. Pravossoudovitch | 4 | 689 | 54.12 |
| H. J. Wunderlich | 5 | 52 | 3.16 |