Paper Info
Title
A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS
Abstract
A next generation VLIW DSP Central Processing Unit (CPU) which has an integrated fixed point and floating point Instruction Set Architecture (ISA) is presented. It is designed to meet a 1.5 GHz core clock frequency in a 40nm process with aggressive area and power goals. In this paper, the benchmarking process and benefits of newly defined instructions such as complex matrix multiply is explained. Also, the CPU data path is described in detail, highlighting several novel micro-architecture features. Finally, our design methodology as well as verification methodology to ensure functional correctness utilizing formal equivalent verification is described.
Year
DOI
Venue
2011
10.1109/ARITH.2011.20
IEEE Symposium on Computer Arithmetic
Keywords
Field
DocType
CMOS integrated circuits,fixed point arithmetic,floating point arithmetic,formal verification,instruction sets,CMOS,ISA,clock frequency,complex matrix multiply,floating point instruction set architecture,formal equivalent verification,frequency 1.5 GHz,integrated fixed point instruction set architecture,micro-architecture,next generation VLIW DSP central processing unit,size 40 nm,Additions,CPU,Complex Matrix Multiply,DSP,Fixed Point,Floating Point,Formal Verification,Multiply,SIMD
Central processing unit,Fixed-point arithmetic,Very long instruction word,Computer science,Instruction set,Floating point,Parallel computing,SIMD,Computer hardware,Clock rate,Formal verification
Conference
ISSN
Citations 
PageRank 
1063-6889
1
0.35
References 
Authors
2
11
Name
Order
Citations
PageRank
Timothy Anderson110.35
Duc Bui2444.34
Shriram Moharil3111.65
Soujanya Narnur410.35
Mujibur Rahman5112.32
Anthony Lell610.35
Eric Biscondi7251.65
Ashish Shrivastava817213.32
Peter Dent910.69
Mingjian Yan1010.35
Hasan Mahmood1110.35