Name
Abstract | ||
|---|---|---|
This paper describes implementation of a part of JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) on a FPGA board using dynamic reconfiguration. Comparison between static and dynamic reconfiguration is presented and new analysis criteria (time performance. logic cost. spatio-temporal efficiency) are defined. MQ-decoder and arithmetic decoder can be classified in the most attractive case for dynamic reconfiguration implementation: applications without parallelism by functions. This implementation is done on an architecture designed to study dynamic reconfiguration of FPGAs: the ARDOISE architecture. The implementation obtained based on four partial configurations of arithmetic decoder allows reducing significantly the number of logic cells (57%) in comparison with static implementation. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ICIP.2004.1421696 | ICIP: 2004 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOLS 1- 5 |
Keywords | Field | DocType |
field programmable gate arrays,decoding,data compression | Computer science,Arithmetic,Field-programmable gate array,Image coding,Soft-decision decoder,Decoding methods,JPEG 2000,Data compression,Control reconfiguration | Conference |
ISSN | Citations | PageRank |
1522-4880 | 1 | 0.35 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sophie Bouchoux | 1 | 8 | 1.29 |
| El-Bay Bourennane | 2 | 89 | 20.58 |
| Michel Paindavoine | 3 | 115 | 21.70 |