| A templated programmable architecture for highly constrained embedded HD video processing | 0 | 0.34 | 2019 |
| Pneuro: A Scalable Energy-Efficient Programmable Hardware Accelerator For Neural Networks | 0 | 0.34 | 2018 |
| Exploration and design of embedded systems including neural algorithms | 0 | 0.34 | 2015 |
| Use of wavelet for image processing in smart cameras with low hardware resources | 2 | 0.38 | 2013 |
| Computational evidence that frequency trajectory theory does not oppose but emerges from age-of-acquisition theory. | 0 | 0.34 | 2012 |
| Development of Active Pixel Photodiode Sensors for Gamma Camera Application | 0 | 0.34 | 2011 |
| The eISP low-power and tiny silicon footprint programmable video architecture | 0 | 0.34 | 2011 |
| Design of Thin-Film-Transistor (TFT) arrays using current mirror circuits for Flat Panel Detectors (FPDs) | 0 | 0.34 | 2011 |
| Processeur vidéo programmable pour la téléphonie mobile eISP, une architecture de calcul très basse consommation à faible empreinte silicium pour le traitement vidéo HD | 0 | 0.34 | 2010 |
| Fast and robust face detection on a parallel optimized architecture implemented on FPGA | 10 | 0.56 | 2009 |
| A 10 000 fps CMOS Sensor With Massively Parallel Image Processing | 36 | 2.39 | 2008 |
| Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6µm CMOS Process | 0 | 0.34 | 2008 |
| An SIMD programmable vision chip with high-speed focal plane image processing | 1 | 0.38 | 2008 |
| CMOS Photodiode Design for Gamma Camera Application | 0 | 0.34 | 2008 |
| A 8 bits Pipeline Analog to Digital Converter Design for High Speed Camera Application | 0 | 0.34 | 2008 |
| Design of a real-time face detection parallel architecture using high-level synthesis | 5 | 0.63 | 2008 |
| Simple imaging system to measure velocity and improve the quality of fertilizer spreading in agriculture | 0 | 0.34 | 2008 |
| Development of Face Recognition System Using Multi-views Database | 0 | 0.34 | 2007 |
| Multiple modular very long instruction word processors based on field programmable gate arrays | 0 | 0.34 | 2007 |
| A Parallel Face Detection System Implemented on FPGA | 4 | 0.56 | 2007 |
| Real-Time 3D Face Acquisition Using Reconfigurable Hybrid Architecture. | 1 | 0.35 | 2007 |
| A Modular Vliw Processor | 8 | 0.82 | 2007 |
| A real-time shot cut detector: Hardware implementation | 4 | 0.51 | 2007 |
| Real-time flaw detection on a complex object: comparison of results using classification with a support vector machine, boosting, and hyperrectangle-based method | 0 | 0.34 | 2006 |
| SystemC design of a smart camera | 0 | 0.34 | 2006 |
| VLSI design of a high-speed CMOS image sensor with in-situ 2D programmable processing | 0 | 0.34 | 2006 |
| Design of a 10000 Frames/s CMOS Sensor with In Situ Image Processing | 1 | 0.37 | 2006 |
| Fast Image Mosaicing for Panoramic Face Recognition | 3 | 0.40 | 2006 |
| The rapid prototyping experiences of image processing algorithms on FPGA | 1 | 0.51 | 2006 |
| Embedded system prototyping experience using multi-DSP VHDL model | 0 | 0.34 | 2006 |
| Embedded image processing/compression for high-speed CMOS sensor | 0 | 0.34 | 2006 |
| Panoramic face mosaicing and recognition using multi-cameras | 0 | 0.34 | 2005 |
| Smart camera design for intensive embedded computing | 5 | 0.52 | 2005 |
| Principles of a CMOS Sensor Dedicated to Face Tracking and Recognition | 1 | 0.48 | 2005 |
| Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA | 2 | 0.40 | 2004 |
| Implementation Of Jpeg2000 Arithmetic Decoder Using Dynamic Reconfiguration Of Fpga | 1 | 0.35 | 2004 |
| Real Time Image Rotation Using Dynamic Reconfiguration | 5 | 0.54 | 2002 |
| Generalization of Canny-Deriche filter for detection of noisy exponential edge. | 11 | 0.74 | 2002 |
| Real time implementation of a face tracking | 1 | 0.38 | 2002 |
| Approximation of the Karhunen–Loève transformation and its application to colour images | 7 | 0.94 | 2001 |
| A principal component analysis based method for the Simulation of turbulence-degraded infrared image sequence | 1 | 0.48 | 1999 |
| Implementation of a real time image rotation using B-spline interpolation on FPGA's board | 4 | 0.45 | 1998 |
| Parallel implementation of a face location algorithm based on the hough transformation | 0 | 0.34 | 1998 |
| Face recognition: pre-processing techniques for linear autoassociators | 0 | 0.34 | 1998 |
| Real time image rotation using B-spline interpolation on FPGA's board | 0 | 0.34 | 1998 |
| A Pre-Processing Technique Based on the Wavelet Transform for Linear Autoassociators with Applications to Face Recognition | 0 | 0.34 | 1997 |
| Multiscale edges detection algorithm implementation using FPGA devices | 1 | 0.44 | 1996 |
