Name
Abstract | ||
|---|---|---|
In synchronous sequential circuit design, clock gating is recognized as a useful technique to reduce the power consumption. Conventionally, the clock gating is synthesized after high-level synthesis. In this paper, we point out that the module binding in high-level synthesis has a significant impact on the power consumption of gated clock tree. Based on that observation, we use an integer linear program (ILP) to formally formulate the problem. Our objective is to find a module binding solution so that the power consumption (of gated clock tree) can be minimized. It is noteworthy to mention that our work is the first attempt to synthesize the clock gating in the high-level synthesis stage. Benchmark data consistently show that our approach can greatly improve the existing design flow. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1587/elex.5.762 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
electronic design automation, high-level synthesis, gated clock, low power | Clock signal,Clock gating,Computer science,Clock domain crossing,Electronic engineering,Clock skew,Synchronous circuit,Digital clock manager,CPU multiplier,Asynchronous circuit | Journal |
Volume | Issue | ISSN |
5 | 18 | 1349-2543 |
Citations | PageRank | References |
2 | 0.38 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chun-Hua Cheng | 1 | 59 | 12.00 |
| Shih-Hsu Huang | 2 | 203 | 38.89 |
| Wen-Pin Tu | 3 | 21 | 4.32 |