Name
Abstract | ||
|---|---|---|
The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory modules. However, these approaches increase power consumption and operating temperatures: temperatures in existing DRAM modules can rise to over 95°C. Another important property of DRAM temperature is the large variation in DRAM chip temperatures. In this paper, we present our analysis collected from measurements on a real system indicating that temperatures across DRAM chips can vary by over 10°C. This work aims to minimize this variation as well as the peak DRAM temperature. We first develop a thermal model to estimate the temperature of DRAM chips and validate this model against real temperature measurements. We then propose three hardware and software schemes to reduce peak temperatures. The first technique introduces a new cache line replacement policy that reduces the number of accesses to the overheating DRAM chips. The second technique utilizes a Memory Write Buffer to improve the access efficiency of the overheated chips. The third scheme intelligently allocates pages to relatively cooler ranks of the DIMM. Our experiments show that in a high performance memory system, our schemes reduce the peak DRAM chip temperature by as much as 8.39°C over 10 workloads (5.36°C on average). Our schemes also improve performance mainly due to reduction in thermal emergencies: for a baseline system with memory bandwidth throttling scheme, the IPC is improved by as much as 15.8% (4.1% on average). |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/HPCA.2011.5749756 | HPCA |
Keywords | Field | DocType |
cache line replacement policy,power aware computing,power consumption,memory write buffer,thermal model,cache storage,dram thermal management,hardware-software techniques,memory modules,dram chip temperature,dram temperature,dram performance,dram chip,high performance memory system,dram performance improvement,thermal management (packaging),dram chips,performance evaluation,dram module,temperature measurements,software technique,overall system performance,peak dram chip temperature,overheating dram chip,peak dram temperature,temperature,temperature measurement,chip,thermal management,system performance,memory bandwidth,registers | Dram,Memory bandwidth,CPU cache,Computer science,Parallel computing,Write buffer,Real-time computing,Static random-access memory,Universal memory,CAS latency,Memory controller,Embedded system | Conference |
ISSN | ISBN | Citations |
1530-0897 | 978-1-4244-9432-3 | 15 |
PageRank | References | Authors |
0.76 | 16 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Song Liu | 1 | 216 | 8.86 |
| Brian Leung | 2 | 15 | 0.76 |
| Alexander Neckar | 3 | 40 | 2.58 |
| Seda Öǧrenci Memik | 4 | 488 | 42.57 |
| Gokhan Memik | 5 | 1694 | 111.88 |
| Nikos Hardavellas | 6 | 1015 | 44.39 |