| Thermal Management for FPGA Nodes in HPC Systems | 0 | 0.34 | 2020 |
| A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree. | 0 | 0.34 | 2020 |
| A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. | 0 | 0.34 | 2019 |
| Machine Learning-Based Temperature Prediction for Runtime Thermal Management Across System Components. | 9 | 0.50 | 2018 |
| Minimizing Thermal Variation in Heterogeneous HPC Systems with FPGA Nodes | 1 | 0.35 | 2018 |
| Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches. | 2 | 0.37 | 2017 |
| A Partial Carry-Save On-the-fly Correction Multispeculative Multiplier | 3 | 0.40 | 2016 |
| Lazy Pipelines: Enhancing quality in approximate computing. | 3 | 0.43 | 2016 |
| A methodology for power characterization of associative memories | 2 | 0.41 | 2015 |
| On-Chip Integration Of Thermoelectric Energy Harvesting In 3d Ics | 0 | 0.34 | 2015 |
| User-specific skin temperature-aware DVFS for smartphones | 3 | 0.40 | 2015 |
| Edge importance identification for energy efficient graph processing | 0 | 0.34 | 2015 |
| b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units | 11 | 0.59 | 2015 |
| Minimizing Thermal Variation Across System Components | 8 | 0.56 | 2015 |
| Editorial | 0 | 0.34 | 2014 |
| Improving circuit performance with multispeculative additive trees in high-level synthesis. | 3 | 0.41 | 2014 |
| A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths | 0 | 0.34 | 2013 |
| Exploring super-resolution implementations across multiple platforms. | 5 | 0.39 | 2013 |
| Exploring the energy efficiency of Multispeculative Adders. | 1 | 0.36 | 2013 |
| Theory and Analysis for Optimization of On-Chip Thermoelectric Cooling Systems | 2 | 0.41 | 2013 |
| Integrating thermocouple sensors into 3D ICs | 3 | 0.40 | 2013 |
| Multispeculative additive trees in high-level synthesis | 3 | 0.40 | 2013 |
| Multispeculative Addition Applied to Datapath Synthesis. | 11 | 0.70 | 2012 |
| A Comprehensive Tapered buffer optimization algorithm for unified design metrics | 1 | 0.43 | 2011 |
| Hardware/software techniques for DRAM thermal management | 15 | 0.76 | 2011 |
| Power optimization in heterogenous datapaths. | 0 | 0.34 | 2011 |
| An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs | 4 | 0.63 | 2010 |
| Using speculative functional units in high level synthesis | 5 | 0.47 | 2010 |
| Placement and Floorplanning in Dynamically Reconfigurable FPGAs | 22 | 0.97 | 2010 |
| An approach for adaptive DRAM temperature and power management | 4 | 0.43 | 2010 |
| Inversed Temperature Dependence aware clock skew scheduling for sequential circuits | 1 | 0.37 | 2010 |
| SACTA: a self-adjusting clock tree architecture for adapting to thermal-induced delay variation | 4 | 0.47 | 2010 |
| A Fast Heuristic Algorithm for Multidomain Clock Skew Scheduling | 5 | 0.48 | 2010 |
| Optimization of the bias current network for accurate on-chip thermal monitoring | 0 | 0.34 | 2010 |
| A framework for optimizing thermoelectric active cooling systems | 8 | 0.75 | 2010 |
| A revisit to the primal-dual based clock skew scheduling algorithm | 2 | 0.41 | 2010 |
| Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers | 7 | 0.79 | 2010 |
| FPGA Implementation of the Interior-Point Algorithm with Applications to Collision Detection | 5 | 0.50 | 2009 |
| An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction | 5 | 0.49 | 2008 |
| A power and temperature aware DRAM architecture | 11 | 0.71 | 2008 |
| Thermal monitoring mechanisms for chip multiprocessors | 28 | 1.20 | 2008 |
| An Approach for Adaptive DRAM Temperature and Power Management | 6 | 0.48 | 2008 |
| Towards An "Early Neural Circuit Simulator": A Fpga Implementation Of Processing In The Rat Whisker System | 2 | 0.47 | 2008 |
| Leakage power-aware clock skew scheduling: Converting stolen time into leakage power reduction | 5 | 0.49 | 2008 |
| Automated design of self-adjusting pipelines | 2 | 0.39 | 2008 |
| A high-level clustering algorithm targeting dual Vdd FPGAs | 0 | 0.34 | 2008 |
| A novel SoC design methodology combining adaptive software and reconfigurable hardware | 12 | 0.64 | 2007 |
| A self-adjusting clock tree architecture to cope with temperature variations | 8 | 0.61 | 2007 |
| Early planning for clock skew scheduling during register binding | 4 | 0.49 | 2007 |
| Self-heating-aware optimal wire sizing under Elmore delay model | 2 | 0.36 | 2007 |
