Abstract | ||
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A new BIST TPG design, called low-transition random TPG (LT-RTPG), that is comprised of an LFSR,a k-input AND gate, and a T flip-flop, is presented.When used to generate test patterns for test-per-scanBIST, it decreases the number of transitions that occur during scan shifting and hence decreases the heatdissipated during testing. Various properties of LT-RTPG's are studied and a methodology for their designis presented. Experimental results demonstrate thatLT-RTPG's designed using the proposed methodologydecrease the heat dissipated during BIST by significantamounts while attaining high fault coverage, especiallyfor circuits with moderate to large number of scan inputs. |
Year | DOI | Venue |
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1999 | 10.1109/TEST.1999.805617 | ITC |
Keywords | Field | DocType |
various property,new bist tpg design,proposed methodologydecrease,low-transition random tpg,high fault coverage,especiallyfor circuit,new test-per-scan bist tpg,large number,low heat dissipation,test pattern,inductance,shift registers,fault coverage,automatic test pattern generation,temperature,design for testability,lfsr | Design for testing,Automatic test pattern generation,Shift register,Inductance,Fault coverage,Computer science,Electronic engineering,Real-time computing,Electronic circuit,AND gate,Built-in self-test | Conference |
ISBN | Citations | PageRank |
0-7803-5753-1 | 42 | 4.61 |
References | Authors | |
7 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Seongmoon Wang | 1 | 605 | 48.50 |
Sandeep K. Gupta | 2 | 1980 | 229.01 |