| An Efficient Method To Screen Resistive Opens Under Presence Of Process Variation | 0 | 0.34 | 2011 |
| A Low Hardware Overhead Self-Diagnosis Technique Using Reed-Solomon Codes for Self-Repairing Chips | 5 | 0.58 | 2010 |
| A low overhead high test compression technique using pattern clustering with n-detection test support | 3 | 0.45 | 2010 |
| Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chip | 22 | 0.83 | 2009 |
| Machine learning-based volume diagnosis | 10 | 0.55 | 2009 |
| X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors | 15 | 0.68 | 2008 |
| Cost Efficient Methods to Improve Performance of Broadcast Scan | 3 | 0.39 | 2008 |
| An Efficient Unknown BlockingScheme for Low Control Data Volume and High Observability | 0 | 0.34 | 2008 |
| Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns | 11 | 0.69 | 2008 |
| Zero Cost Test Point Insertion Technique for Structured ASICs | 1 | 0.35 | 2007 |
| SoC Testing Using LFSR Reseeding, and Scan-Slice- Based TAM Optimization and Test Scheduling | 4 | 0.49 | 2007 |
| A hybrid scheme for compacting test responses with unknown values | 2 | 0.37 | 2007 |
| Unknown blocking scheme for low control data volume and high observability | 10 | 0.55 | 2007 |
| A BIST TPG for Low Power Dissipation and High Fault Coverage | 15 | 0.74 | 2007 |
| A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture | 21 | 0.98 | 2007 |
| PIDISC: Pattern Independent Design Independent Seed Compression Technique | 7 | 0.54 | 2006 |
| LT-RTPG: a new test-per-scan BIST TPG for low switching activity | 14 | 0.74 | 2006 |
| Unknown-tolerance analysis and test-quality control for test response compaction using space compactors | 4 | 0.41 | 2006 |
| Coverage loss by using space compactors in presence of unknown values | 0 | 0.34 | 2006 |
| Efficient unknown blocking using LFSR reseeding | 2 | 0.41 | 2006 |
| XWRC: externally-loaded weighted random pattern testing for input test data compression | 5 | 0.48 | 2005 |
| ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values | 5 | 0.52 | 2005 |
| Response shaper: a novel technique to enhance unknown tolerance for output response compaction | 25 | 0.93 | 2005 |
| Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage | 10 | 0.80 | 2005 |
| Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets | 63 | 3.15 | 2004 |
| Re-configurable embedded core test protocol | 2 | 0.53 | 2004 |
| A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs | 8 | 0.53 | 2003 |
| An automatic test pattern generator for minimizing switching activity during scan testing activity | 30 | 1.09 | 2002 |
| Generation of low power dissipation and high fault coverage patterns for scan-based BIST | 32 | 1.49 | 2002 |
| LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation | 42 | 4.61 | 1999 |
| ATPG for heat dissipation minimization during scan testing | 58 | 6.01 | 1997 |
| DS-LFSR: a new BIST TPG for low heat dissipation | 57 | 6.22 | 1997 |
| ATPG for heat dissipation minimization during test application | 119 | 11.39 | 1994 |
