Name
Abstract | ||
|---|---|---|
A new built-in self-test (BIST) test pattern generator (TPG) design, called low-transition random TPG (LT-RTPG), is presented. An LT-RTPG is composed of a linear feedback shift register (LFSR), a κ-input AND gate, and a T flip-flop. When used to generate test patterns for test-per-scan BIST, it decreases the number of transitions that occur during scan shifting and, hence, decreases switching activity during testing. Various properties of LT-RTPGs are identified and a methodology for their design is presented. Experimental results demonstrate that LT-RTPGs designed using the proposed methodology decrease switching activity during BIST by significant amounts while providing high fault coverage. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TCAD.2005.855927 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
new test-per-scan,integrated circuit testing,low switching activity,test pattern generator,switching activity,test pattern,proposed methodology decrease,test pattern generator (TPG),significant amount,LFSR,automatic test pattern generation,testing,shift registers,new built-in self-test,built-in self test,built-in self-test,high fault coverage,heat dissipation during testing,BIST TPG,Built-in self-test (BIST),low-transition random tpg,flip-flops,k-input AND gate,low-transition random TPG,linear feedback shift register,T flip-flop,switching circuits,logic gates,test-per-scan bist,LT-RTPG,bist tpg | Journal | 25 |
Issue | ISSN | Citations |
8 | 0278-0070 | 14 |
PageRank | References | Authors |
0.74 | 12 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seongmoon Wang | 1 | 605 | 48.50 |
| S. K. Gupta | 2 | 274 | 42.67 |