Name
Abstract | ||
|---|---|---|
In this paper, a novel hybrid fault tolerant architecture for digital circuits is proposed in order to enable the use of future CMOS technology nodes. This architecture targets robustness, power consumption and yield at the same time, at area costs comparable to standard fault tolerance schemes. The architecture increases circuit robustness by tolerating both transient and permanent online faults. It consumes less power than the classical Triple Modular Redundancy (TMR) approach while utilizing comparable silicon area. It overcomes many permanent faults occurring throughout manufacturing while still tolerating soft errors introduced by particle strikes. These can be done by using scalable redundancy resources, while keeping the hardened combinational logic circuits intact. The technique combines different types of redundancy: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error tolerance. Results on largest ISCAS and ITC benchmark circuits show that our approach has an area cost negligible of about 2% to 3% with a power consumption saving of about 30% compared to TMR. Finally, it deals with aging phenomenon and thus, increases the expected lifetime of logic circuits. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ATS.2011.89 | Asian Test Symposium |
Keywords | Field | DocType |
CMOS logic circuits,error detection,fault tolerance,redundancy,CMOS technology,ISCAS benchmark circuit,ITC benchmark circuit,circuit robustness improvement,classical triple modular redundancy approach,combinational logic circuit,comparable silicon area,digital circuit,error detection,hard error tolerance,hybrid fault tolerant architecture,information redundancy,permanent online fault,power consumption,scalable redundancy resource,soft error,TMR,aging phenomenon,fault tolerance,permanent error,power consumption,robustness,transient error | Digital electronics,Soft error,Computer science,Triple modular redundancy,Real-time computing,Robustness (computer science),Electronic engineering,Error detection and correction,Redundancy (engineering),Fault tolerance,Dual modular redundancy,Embedded system | Conference |
ISSN | Citations | PageRank |
1081-7735 | 4 | 0.53 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. A. Tran | 1 | 212 | 11.30 |
| A. Virazel | 2 | 169 | 23.25 |
| A. Bosio | 3 | 113 | 15.51 |
| L. Dilillo | 4 | 44 | 9.49 |
| P. Girard | 5 | 478 | 41.91 |
| S. Pravossoudovitch | 6 | 689 | 54.12 |
| H.-J. Wunderlich | 7 | 62 | 6.60 |