Title
A nonlinearity error calibration technique for pipelined ADCs
Abstract
This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.
Year
DOI
Venue
2011
10.1016/j.vlsi.2011.01.004
Integration
Keywords
Field
DocType
chopping technique,extra adc,digital background calibration technique,nonlinearity error calibration technique,high resolution reference adcs,current work,pipelined adcs,digital converter,pipelined adc,background calibration,main adc architecture,harmonic distortion,main trend,simple two-step subranging adc,conventional calibration method,main adc,high resolution,technology
Data point,Flight dynamics (spacecraft),Total harmonic distortion,Computer science,Analog-to-digital converter,Effective number of bits,Electronic engineering,Successive approximation ADC,Offset (computer science),Calibration
Journal
Volume
Issue
ISSN
44
3
Integration, the VLSI Journal
Citations 
PageRank 
References 
0
0.34
18
Authors
4
Name
Order
Citations
PageRank
Armin Jalili172.20
Sayed Masoud Sayedi2479.88
J. Jacob Wikner33217.14
Abolghasem Zeidaabadi Nezhad411.71