Sayed Masoud Sayedi

Author Info

Name	Affiliation	Papers
SAYED MASOUD SAYEDI	Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan 84156-83111, Iran	25
Collaborators	Citations	PageRank
24	47	9.88
Referers	Referees	References
94	599	288

Search Limit

100599

Publications (25 rows)

Collaborators (24 rows)

Referers (94 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A structured review of sparse fast Fourier transform algorithms	0	0.34	2022
Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals.	0	0.34	2018
A Low-Complexity Hardware for Deterministic Compressive Sensing Reconstruction.	1	0.36	2018
SystemC-AMS modeling of photodiode based on PWL technique to be used in energy harvesting CMOS image sensor.	0	0.34	2018
High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves.	3	0.38	2017
Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications.	1	0.37	2017
Color-based skin segmentation in videos using a multi-step spatial method.	2	0.38	2017
Efficient and low-complexity hardware architecture of Gaussian normal basis multiplication over GF(2 m ) for elliptic curve cryptosystems.	6	0.45	2017
High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2 m ).	4	0.46	2017
An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m).	0	0.34	2016
High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m).	1	0.35	2016
A low-power wide tuning-range CMOS current-controlled oscillator.	2	0.39	2016
High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems.	6	0.45	2016
A face detection method based on kernel probability map	2	0.38	2015
Efficient Implementation Of Low Time Complexity And Pipelined Bit-Parallel Polynomial Basis Multiplier Over Binary Finite Fields	0	0.34	2015
FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm	11	0.63	2014
Implementation of a low power 16-bit radix-4 pipelined SRT divider using a modified Split-Path Data Driven Dynamic Logic (SPD3L) structure	0	0.34	2013
A low power D3L 16-bit radix- 4 pipelined SRT divider.	0	0.34	2012
Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs	4	0.43	2011
A nonlinearity error calibration technique for pipelined ADCs	0	0.34	2011
Calibration of high-resolution flash ADCS based on histogram test methods.	0	0.34	2010
Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop	0	0.34	2009
A frequency based digital background calibration technique for pipelined ADCs.	0	0.34	2008
A 1.2V current-mode true RMS-DC converter based on the floating gate MOS translinear principle	4	0.78	2008
A Novel Digital Voltage Controller For Single-Phase Pfc Rectifiers	0	0.34	2006