Name
Abstract | ||
|---|---|---|
During the very large scale integration design process, a synthesized design is often required to be modified in order to accommodate different goals. To preserve the engineering effort already invested, designers seek small logic structural transformations to achieve these logic restructuring goals. This paper proposes a systematic methodology to devise such transformations automatically. It first presents a simulation-based formulation to approximate sets of pairs of functions to be distinguished and avoid the memory/time explosion issue inherent with the original representation. Then, it uses this new data structure to devise the required transformations dynamically without the need of a static dictionary model. The methodology is applied to both combinational and sequential designs with transformations at a single or multiple locations. An extensive suite of experiments documents the benefits of the proposed methodology when compared to existing practices. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TCAD.2011.2110590 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
sequential circuits,logic restructuring,automating logic transformations,logic rewire,synthesized design,combinational circuits,approximate spfds,engineering change,logic structural transformation,required transformations dynamically,combinational design,very large scale integration,sequential design,circuit optimisation,data structure,large scale integration design,debug,small logic,memory-time explosion,very large scale integration design,approximate set,different goal,optimization,logic design,VLSI,integrated circuit design,logic restructuring goal,SPFD,systematic methodology,Correction,proposed methodology,simulation-based formulation | Journal | 30 |
Issue | ISSN | Citations |
5 | 0278-0070 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yu-Shen Yang | 1 | 92 | 8.23 |
| S. Sinha | 2 | 19 | 1.31 |
| A. Veneris | 3 | 937 | 67.52 |
| Robert K. Brayton | 4 | 6224 | 883.32 |