Yu-Shen Yang - Citegraph

Author Info

Name	Affiliation	Papers
YU-SHEN YANG	Vennsa Technologies Inc., Toronto, ON, Canada	15
Collaborators	Citations	PageRank
18	92	8.23
Referers	Referees	References
168	250	205

Search Limit

100250

Publications (15 rows)

Collaborators (18 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Simulation and satisfiability guided counter-example triage for RTL design debugging	4	0.54	2014
A failure triage engine based on error trace signature extraction	2	0.38	2013
Leveraging reconfigurability to raise productivity in FPGA functional debug	2	0.40	2012
Automated data analysis techniques for a modern silicon debug environment	3	0.41	2012
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment	6	0.63	2012
Automating Logic Transformations With Approximate SPFDs	0	0.34	2011
Automated silicon debug data analysis techniques for a hardware data acquisition environment	5	0.48	2010
Automated data analysis solutions to silicon debug	18	0.78	2009
Sequential logic rectifications with approximate SPFDs	0	0.34	2009
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD	3	0.40	2008
Automating Logic Rectification by Approximate SPFDs	19	0.97	2007
Seamless Integration of SER in Rewiring-Based Design Space Exploration	23	1.22	2006
Extraction error modeling and automated model debugging in high-performance custom designs	2	0.39	2006
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs	2	0.40	2005
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs	3	0.56	2003

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