Paper Info
Title
Asymmetric-access aware optimization for STT-RAM caches with process variations
Abstract
STT-RAM (Spin Transfer Torque Random Access Memory) has been extensively researched as a potential replacement of SRAM (Static RAM) as on-chip caches. Prior work has shown that STT-RAM caches can improve performance and reduce power consumption because of its advantages of high density, fast read speed, low standby power, etc. However, under the impact of process variations, using worst-case design can induce significant performance and power overhead in STT-RAM caches. In order to overcome the problem of process variations, we propose to apply the variable-latency access method to STT-RAM caches by introducing a variation-aware LRU (Least Recently Used) policy. Moreover, we show that simply applying traditional variable-latency access method is inefficient due to the read/write asymmetry. First, we demonstrate that a write-oriented data migration is preferred. Second, a block remapping is necessary to prevent some cache sets from being significantly affected by process variations. After using our techniques, the experimental results show that the performance can be improved by 13.8% and power consumption can be reduced by 14.1% compared to a prior approach [3].
Year
DOI
Venue
2013
10.1145/2483028.2483079
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
low standby power,significant performance,power overhead,process variation,stt-ram cache,variable-latency access method,prior work,power consumption,asymmetric-access aware optimization,traditional variable-latency access method,prior approach
Tag RAM,Standby power,Access method,Computer science,Cache,Parallel computing,Real-time computing,False sharing,Static random-access memory,Cache algorithms,Random access
Conference
Citations 
PageRank 
References 
4
0.44
13
Authors
5
Name
Order
Citations
PageRank
Yi Zhou16517.55
Chao Zhang242338.17
Guangyu Sun31920111.55
Kun Wang47914.33
Yu Zhang5503.32