Name
Affiliation
Papers
GUANGYU SUN
Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA
127
Collaborators
Citations 
PageRank 
301
1920
111.55
Referers 
Referees 
References 
4131
3144
1423
Search Limit
1001000
Title
Citations
PageRank
Year
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping.00.342022
Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network00.342022
PTQ4ViT: Post-training Quantization for Vision Transformers with Twin Uniform Quantization.00.342022
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique.00.342022
PetS: A Unified Framework for Parameter-Efficient Transformers Serving00.342022
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices00.342021
STAR: Synthesis of Stateful Logic in RRAM Targeting High ARea Utilization00.342021
Nas4rram: Neural Network Architecture Search For Inference On Rram-Based Accelerators20.382021
SaFace: Towards Scenario-aware Face Recognition via Edge Computing System.00.342020
Characterizing Membership Privacy In Stochastic Gradient Langevin Dynamics00.342020
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks.00.342020
MobiLattice - A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.10.432020
Hardware-Assisted Service Live Migration In Resource-Limited Edge Computing Systems00.342020
Edge-Stream: a Stream Processing Approach for Distributed Applications on a Hierarchical Edge-computing System00.342020
Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs00.342020
S2DNAS: Transforming Static CNN Model for Dynamic Inference via Neural Architecture Search00.342020
RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses.30.412019
P3sgd: Patient Privacy Preserving Sgd For Regularizing Deep Cnns In Pathological Image Classification10.362019
GraphH: A Processing-in-Memory Architecture for Large-scale Graph Processing100.532019
ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory10.362019
Accelerate service live migration in resource-limited edge computing systems.00.342019
Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design00.342019
BAYHENN: Combining Bayesian Deep Learning and Homomorphic Encryption for Secure DNN Inference.40.462019
Joint Task Assignment, Transmission, And Computing Resource Allocation In Multilayer Mobile Edge Computing Systems60.412019
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks.160.862019
Optimizing Cache Bypassing and Warp Scheduling for GPUs.30.392018
HPC Software and Programming Environments for Big Data Applications.10.342018
Shadow Block - Accelerating ORAM Accesses with Data Duplication.50.482018
CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs.50.402018
PM3: Power Modeling and Power Management for Processing-in-Memory00.342018
Path Prefetching: Accelerating Index Searches for In-Memory Databases00.342018
G2C: A Generator-to-Classifier Framework Integrating Multi-Stained Visual Cues for Pathological Glomerulus Classification.00.342018
RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases10.362018
V-PIM: An Analytical Overhead Model for Processing-in-Memory Architectures10.352018
Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/miss.00.342017
Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective.00.342017
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates421.792017
Hierarchical RNN Networks for Structured Semantic Web API Model Learning and Extraction00.342017
SRPGAN: Perceptual Generative Adversarial Network for Single Image Super Resolution.10.362017
Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes.20.422017
Toss-up Wear Leveling: Protecting Phase-Change Memories from Inconsistent Write Patterns.10.382017
Accelerate context switch by racetrack-SRAM hybrid cells00.342016
Exploring Main Memory Design Based on Racetrack Memory Technology.60.492016
Performance-centric register file design for GPUs using racetrack memory50.422016
The Applications of NVM Technology in Hardware Security.20.362016
Statistical Cache Bypassing for Non-Volatile Memory.30.412016
PDS: pseudo-differential sensing scheme for STT-MRAM.10.352016
np-ECC: Nonadjacent position error correction code for racetrack memory00.342016
A novel PUF based on cell error rate distribution of STT-RAM10.352016
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power210.922015
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