Paper Info
Title
Synchronous Elasticization: Considerations For Correct Implementation And Minimips Case Study
Abstract
Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elasticization is one approach (among others) of transforming an ordinary clocked circuit into a latency insensitive design. This paper presents practical considerations of elasticizing reconvergent fanouts. It also investigates the suitability of previously published as well as new join and fork implementations for usage in the elastic control network. We demonstrate that elasticization comes at a cost. Measurements of a MiniMIPS processor fabricated in a 0.5 mu m node show that elasticization results in area and dynamic and idle power penalties of 29%, 13% and 58.3%, respectively, without any loss in performance. These measurements do not exploit the capability of pipeline bubbles that occur if one needs to have unpredictable interface latency, or to insert extra bubbles into a pipeline due to wire delays. We finally show the architectural performance advantage of eager over lazy protocols in the presence of bubbles in the MiniMIPS.
Year
DOI
Venue
2010
10.1109/VLSISOC.2010.5642631
PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP
Keywords
Field
DocType
SOC, Synchronous Elasticity, Latency Insensitive Design, MiniMIPS
Fork (system call),Logic gate,Synchronization,System on a chip,Design paradigm,Latency (engineering),Computer science,Robustness (computer science),Integrated circuit design,Embedded system
Conference
Citations 
PageRank 
References 
3
0.44
0
Authors
3
Name
Order
Citations
PageRank
Eliyah Kilada161.19
Shomit Das291.97
Kenneth S. Stevens318525.65