| A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols | 0 | 0.34 | 2019 |
| Low Power SPI Design Based on Relative Timing Techniques | 0 | 0.34 | 2019 |
| Physical Design Variation in Relative Timed Asynchronous Circuits | 0 | 0.34 | 2017 |
| Design of a low power, relative timing based asynchronous MSP430 microprocessor. | 0 | 0.34 | 2017 |
| Design of a multi-style and multi-frequency FPGA | 0 | 0.34 | 2016 |
| Qualifying Relative Timing Constraints for Asynchronous Circuits | 3 | 0.39 | 2016 |
| Path Based Timing Validation For Timed Asynchronous Design | 4 | 0.47 | 2016 |
| Reconfigurable circuit for implementation of family of 4-phase latch protocols | 0 | 0.34 | 2016 |
| Timing Path-Driven Cycle Cutting for Sequential Controllers. | 0 | 0.34 | 2016 |
| A Design Space and its Patterns: Modelling 2phase Asynchronous Pipelines. | 1 | 0.37 | 2014 |
| Leveraging The Geometric Properties Of On-Chip Transmission Line Structures To Improve Interconnect Performance: A Case Study In 65nm | 0 | 0.34 | 2013 |
| Symbolic verification of timed asynchronous hardware protocols | 4 | 0.46 | 2013 |
| Relative timing driven multi-synchronous design: enabling order-of-magnitude energy reduction | 0 | 0.34 | 2013 |
| Design of low energy, high performance synchronous and asynchronous 64-point FFT | 9 | 0.69 | 2013 |
| SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead | 0 | 0.34 | 2013 |
| Synchronous elasticization at a reduced cost: utilizing the ultra simple fork and controller merging | 2 | 0.39 | 2011 |
| Link pipelining strategies for an application-specific asynchronous NoC | 5 | 0.43 | 2011 |
| Concurrency Reduction of Untimed Latch Protocols - Theory and Practice | 5 | 0.52 | 2010 |
| Bandwidth optimization in asynchronous NoCs by customizing link wire length | 3 | 0.39 | 2010 |
| Synchronous Elasticization: Considerations For Correct Implementation And Minimips Case Study | 3 | 0.44 | 2010 |
| Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs | 11 | 0.58 | 2010 |
| Design and Verification of Lazy and Hybrid Implementations of the SELF Protocol. | 1 | 0.36 | 2010 |
| The Future of Formal Methods and GALS Design | 6 | 0.52 | 2009 |
| Characterization of Asynchronous Templates for Integration into Clocked CAD Flows | 22 | 1.15 | 2009 |
| Automatic synthesis of computation interference constraints for relative timing verification | 17 | 1.03 | 2009 |
| Radiation Hardening by Design of Asynchronous Logic for Hostile Environments | 4 | 0.69 | 2009 |
| Elastic Flow in an Application Specific Network-on-Chip | 10 | 0.84 | 2008 |
| The Family of 4-phase Latch Protocols | 9 | 0.69 | 2008 |
| Network Simplicity for Latency Insensitive Cores | 1 | 0.36 | 2008 |
| Performance Evaluation of Elastic GALS Interfaces and Network Fabric | 11 | 0.63 | 2008 |
| Dynamic gates with hysteresis and configurable noise tolerance. | 0 | 0.34 | 2007 |
| Guest Editors' Introduction: GALS Design and Validation | 1 | 0.35 | 2007 |
| Algorithms for MIS Vector Generation and Pruning | 1 | 0.37 | 2006 |
| Modeling and Verifying Circuits Using Generalized Relative Timing | 6 | 0.53 | 2005 |
| Energy and Performance Models for Clocked and Asynchronous Communication | 12 | 1.88 | 2003 |
| Lazy Transition Systems And Asynchronous Circuit Synthesis With Relative Timing Assumptions | 4 | 0.48 | 2002 |
| Congruent Weak Conformance, a Partial Order among Processes | 1 | 0.36 | 2002 |
| A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications | 3 | 1.14 | 1998 |
| The Architecture of FAIM-1 | 5 | 0.66 | 1987 |
| The Post Office-Communication Support for Distributed Ensemble Architectures | 21 | 4.74 | 1986 |
