Name
Title | ||
|---|---|---|
A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization |
Abstract | ||
|---|---|---|
Recent work in ultra-low-power sensor platforms has enabled a number of new applications in medical, infrastructure, and environmental monitoring. Due to their limited energy storage volume, these sensors operate with long idle times and ultra-low standby power ranging from 10s of nW down to 100s of pW. Since radio transmission is relatively expensive, even at the lowest reported power of 0.2mW, wireless communication between sensor nodes must be performed infrequently. Accurate measurement of the time interval between communication events (i.e. the synchronization cycle) is of great importance. Inaccuracy in the synchronization cycle time results in a longer period of uncertainty where sensor nodes are required to enable their radios to establish communication (Fig. 2.7.1), quickly making radios dominate the energy budget. Quartz crystal oscillators and CMOS harmonic oscillators exhibit very small sensitivity to supply voltage and temperature but cannot be used in the target application space since they operate at very high frequencies and exhibit power consumption that is several orders of magnitude larger (>;300nW) than the needed idle power. A gate-leakage-based timer was proposed that leveraged small gate leakage currents to achieve power consumption within the required budget (<; 1nW). However, this timer incurs high RMS jitter (1400ppm) and temperature sensitivity (0.16%/oC). A 150pW program-and-hold timer was proposed to reduce temperature sensitivity but its drifting clock frequency limits its use for synchronization. The quality of a timer is not captured well by RMS jitter since it ignores the averaging of jitter over multiple timer clock periods in a single synchronization cycle. Instead, we propose the uncertainty in a single synchronization cycle of length T as new metric and use this synchronization uncertainty (SU) to evaluate different timer approaches. The timer period is a random variable X(n), with mean and sigma, μ and σ. Given a synchronization cycle time T, consisting of N timer periods, we define SU as the standard deviation of T as given by √(T/μ) × σ, assuming X(n) is Gaussian. Note that a smaller clock period increases N and results in more averaging and a lower SU with fixed jitter (σ/μ). |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISSCC.2011.5746213 | ISSCC |
Keywords | Field | DocType |
logic circuits,synchronization cycle,radio transmission,energy storage volume,power 660 pw,low-power electronics,program-and-hold timer,detector circuits,ultralow power wireless sensor node synchronization,wireless sensor networks,power 150 pw,multistage temperature compensated timer,synchronisation,time interval,logic gate,synchronization,temperature measurement,logic gates,low power electronics,uncertainty,jitter,leakage current | Synchronization,Standby power,Computer science,Electronic engineering,CMOS,Timer,Jitter,Oscillator start-up timer,Electrical engineering,Clock rate,Low-power electronics | Conference |
ISSN | ISBN | Citations |
0193-6530 | 978-1-61284-303-2 | 4 |
PageRank | References | Authors |
0.58 | 6 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoonmyung Lee | 1 | 372 | 43.01 |
| Bharan Giridhar | 2 | 76 | 4.93 |
| Zhiyoong Foo | 3 | 278 | 31.67 |
| Dennis Sylvester | 4 | 5295 | 535.53 |
| David Blaauw | 5 | 8916 | 823.47 |