Name
Abstract | ||
|---|---|---|
In this paper, we look into a feasible approach to incorporating caches into selected switching ele ments of a multistage interconnection network (MIN)- based multiprocessor. Along with the processor private caches, these switch caches form a two-level cache hi erarchy. Selected switch caches within a particular stage of the MIN are connected by a coherence con trol bus, through which a write-invalidate cache coher ence protocol is maintained. Considering scalability and practicality issues, only limited inclusion between the two cache levels is enforced. A simulation-based performance study is conducted to analyze the impact of the protocol on system performance. Comparison between limited and strict inclusion shows that system performance declines with limited inclusion. |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/ICPP.1993.13 | ICPP |
Keywords | Field | DocType |
strict inclusion,system performance,selected switch cache,cache level,switch cache,cache coherence protocol,limited inclusion,system performance decline,min-based multiprocessors,simulation-based performance study,two-level cache,processor private cache,parallel processing,discrete event simulation,cache coherence,protocols,scalability,switches | MSI protocol,Cache invalidation,MESIF protocol,Cache,Computer science,Parallel computing,MESI protocol,Computer network,Cache algorithms,Bus sniffing,Cache coherence,Distributed computing | Conference |
ISSN | ISBN | Citations |
0190-3918 | 0-8493-8983-6 | 1 |
PageRank | References | Authors |
0.35 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mazin S. Yousif | 1 | 321 | 20.66 |
| Chita R. Das | 2 | 1038 | 59.34 |
| Matthew J. Thazhuthaveetil | 3 | 355 | 19.38 |