Name
Abstract | ||
|---|---|---|
This paper presents a 35-GS/s, 4-bit flash ADC-DAC with active data and clock distribution trees. At mm-wave clock frequencies, skew due to mismatch in the clock and data distribution paths is a significant challenge for both flash and time-interleaved converter architectures. A full-rate front-end track and hold amplifier (THA) may be used to reduce the effect of skew. However, it is found that the THA output must then be distributed to the comparators with a bandwidth greater than the sampling frequency in order to preserve the flat regions of the track and hold waveform. Instead, if the data and clock distribution have very low skew, the THA can be omitted thus obviating the associated nonlinearities and resulting in improved performance. In this work, a tree of fully symmetric and linear BiCMOS buffers, called a ldquodata treerdquo, distributes the input to the comparator bank with a measured 3-dB bandwidth of 16 GHz. The data tree is integrated into a complete 4-bit ADC including a full-rate input THA that can be disabled and a 4-bit thermometer-code DAC for testing purposes. The chip occupies 2.5 mm times 3.2 mm including pads and is implemented in 0.18 mum SiGe BiCMOS technology. The ADC consumes 4.5 W from a 3.3 V supply while the DAC operates from a 5 V supply and consumes 0.5 W. The ADC has 3.7 ENOB with a 3-dB effective resolution bandwidth of 8 GHz and a full-scale differential input range of 0.24 Vpp. With the THA enabled, the performance degrades rapidly beyond 8 GHz to less than 1-bit, but with the THA disabled, the ENOB remains better than 3-bits for inputs up to 11 GHz with an SFDR of better than 26 dB. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/JSSC.2009.2020657 | Solid-State Circuits, IEEE Journal of |
Keywords | Field | DocType |
bandwidth 3 ghz,thermometer-code dac,clock distribution tree,flash data converters,data distribution path,analogue-digital conversion,active data,mm-wave clock frequencies,flash adc,time-interleaved converter architecture,voltage 3.3 v,linear bicmos buffers,size 3.2 mm,fully symmetric bicmos buffers,bicmos integrated circuits,bicmos amplifiers,sampling frequency,clocks,active clock distribution,power 4.5 w,sige bicmos hbt,active data distribution,full-rate front-end track and hold amplifier,word length 4 bit,voltage 5 v,track and hold amplifier (tha),comparator bank,power 0.5 w,transimpedance amplifier (tia),bandwidth 8 ghz,analog to digital converter (adc),sample and hold circuits,digital to analog converter (dac),flash memories,size 2.5 mm,dsp-based equalizers,mm-wave data converters,coding,spurious free dynamic range,degradation,operational amplifier,comparator circuit,clock,chip,integrated circuit,front end,sample and hold circuit,bandwidth,transimpedance amplifier,digital signal processor,equalizer,time frequency analysis,testing,sampling methods | BiCMOS,Comparator,Computer science,Effective resolution bandwidth,Electronic engineering,Effective number of bits,Flash ADC,Skew,Sample and hold,Electrical engineering,Operational amplifier | Journal |
Volume | Issue | ISSN |
44 | 6 | 0018-9200 |
Citations | PageRank | References |
4 | 0.87 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shahriar Shahramian | 1 | 52 | 8.26 |
| Sorin P. Voinigescu | 2 | 221 | 53.57 |
| Anthony Chan Carusone | 3 | 269 | 42.19 |