Sorin P. Voinigescu

Author Info

Name	Affiliation	Papers
SORIN P. VOINIGESCU	Univ Toronto, Edwards S Rogers Sr Dept Elect & Comp Engn, Toronto, ON, Canada	29
Collaborators	Citations	PageRank
74	221	53.57
Referers	Referees	References
780	308	82

Search Limit

100780

Publications (29 rows)

Collaborators (74 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics Applications	3	0.51	2019
A 4.6V, 6-bit, 64GS/s Transmitter in 22nm FDSOI CMOS	0	0.34	2019
A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications	1	0.48	2018
128-GS/s ADC Front-End with Over 60-GHz Input Bandwidth in 22-nm Si/SiGe FDSOI CMOS	1	0.38	2018
A 256-Gbps PAM-4 Signal Generator IC in <tex>$0.25-\mu \text{m}$</tex> InP DHBT Technology	2	0.42	2018
AD-Band Digital Transmitter with 64-QAM and OFDM Free-Space Constellation Formation.	0	0.34	2018
A 13.2-dBm, 138-GHz I/Q RF-DAC with 64-QAM and OFDM free-space constellation formation.	0	0.34	2017
SiGe HBT Technology: Future Trends and TCAD-Based Roadmap.	1	0.48	2017
Silicon Millimeter-Wave, Terahertz, and High-Speed Fiber-Optic Device and Benchmark Circuit Scaling Through the 2030 ITRS Horizon.	2	0.38	2017
Introduction to the Special Section on the 2016 IEEE BCTM and IEEE CSICS.	0	0.34	2017
A 234-261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4-7.2 dBm Output Power, 1.3% DC-to-RF Efficiency, and 1-GHz Divided-Down Output.	7	0.81	2016
Analog Circuit Blocks for 80-GHz Bandwidth Frequency-Interleaved, Linear, Large-Swing Front-Ends.	0	0.34	2016
55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters.	2	0.58	2016
A 3×60Gb/s Transmitter/Repeater Front-End With 4.3VPP Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology.	0	0.34	2016
A 3×40Gb/s 28nm FDSOI CMOS front-end array with 10mVPP sensitivity and >4VPP output swing.	0	0.34	2015
A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing.	0	0.34	2012
A 2.4-Vpp 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies.	0	0.34	2011
Design of a Dual W- and D-Band PLL	5	0.84	2011
An 18-Gb/s, Direct QPSK Modulation SiGe BiCMOS Transceiver for Last Mile Links in the 70-80 GHz Band.	14	1.60	2010
A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees	4	0.87	2009
A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link	34	5.42	2009
165-GHz Transceiver in SiGe Technology	9	1.70	2008
Towards A Sub-2.5v, 100-Gb/S Serial Transceiver	3	3.04	2007
Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio	75	20.30	2007
Design and Scaling of W-Band SiGe BiCMOS VCOs	13	1.91	2007
65-nm CMOS, W-Band Receivers for Imaging Applications.	2	0.45	2007
A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology	14	2.34	2006
An 80-Gb/S 2(31)-1 Pseudorandom Binary Sequence Generator In Sige Bicmos Technology	11	1.80	2005
A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design	18	6.22	1997