Name
Title | ||
|---|---|---|
Low-Voltage And Low-Power Logic, Memory, And Analog Circuit Techniques For Socs Using 90 Nm Technology And Beyond |
Abstract | ||
|---|---|---|
Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-pA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietele/e89-c.3.250 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
low power, CMOS, SoC, 90 nm, low voltage, variability | Dynamic random-access memory,Dram,Adder,Electronic engineering,CMOS,Low voltage,Engineering,Transistor,Integrated circuit,Electrical engineering,Low-power electronics | Journal |
Volume | Issue | ISSN |
E89C | 3 | 1745-1353 |
Citations | PageRank | References |
4 | 0.49 | 0 |
Authors | ||
14 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Koichiro Ishibashi | 1 | 34 | 8.76 |
| Tetsuya Fujimoto | 2 | 4 | 0.83 |
| Takahiro Yamashita | 3 | 4 | 0.49 |
| Hiroyuki Okada | 4 | 4 | 0.49 |
| Yukio Arima | 5 | 16 | 2.81 |
| Yasuyuki Hashimoto | 6 | 4 | 0.49 |
| Kohji Sakata | 7 | 4 | 0.49 |
| Isao Minematsu | 8 | 4 | 0.49 |
| Yasuo Itoh | 9 | 4 | 0.49 |
| Haruki Toda | 10 | 4 | 0.83 |
| Motoi Ichihashi | 11 | 4 | 1.17 |
| Yoshihide Komatsu | 12 | 26 | 5.22 |
| Masato Hagiwara | 13 | 58 | 7.60 |
| Toshiro Tsukada | 14 | 20 | 4.74 |